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ATF22LV10CQZ-30SC

更新时间： 2024-01-24 16:31:16

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
19页	347K
描述
Highperformance EE PLD

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4.4

Input Test Waveforms

4.4.1

Input Test Waveforms and Measurement Levels

4.4.2

Output Test Loads

Note:

Similar competitors devices are specified with slightly different loads. These load differences may

affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet

compatible device specification conditions.

4.5

4.6

Pin Capacitance

Table 4-1.

Pin Capacitance (f = 1 MHz, T = 25°C⁽¹⁾)

Typ

Max

Units

Conditions

V_IN= 0V

C_IN

C_I/O

V_OUT= 0V

Note:

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%

tested.

Power-up Reset

The registers in the ATF22LV10CZ/CQZ are designed to reset during power-up. At a point

delayed slightly from V_CCcrossing V_RST, all registers will be reset to the low state. The output

state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature

of reset and the uncertainty of how V_CCactually rises in the system, the following conditions are

required:

1. The V_CCrise must be monotonic and start below 0.7V.

2. The clock must remain stable during T_PR

3. After T_PR, all input and feedback setup times must be met before driving the clock pin

high.

4.7

Preload of Register Outputs

The ATF22LV10CZ/CQZ’s registers are provided with circuitry to allow loading of each register

with either a high or a low. This feature will simplify testing since any state can be forced into the

registers to control test sequencing. A JEDEC file with preload is generated when a source file

ATF22LV10C(Q)Z

0779L–PLD–12/05

1...3 4 567 8 9...19

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