Features
• 3.0V to 5.5V Operating Range
• Lowest Power in It Class
• Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device
• “Zero” Standby Power (25 µA Maximum) (Input Transition Detection)
• Low-voltage Equivalent of ATF22V10CZ
• Ideal for Battery Powered Systems
• CMOS- and TTL-compatible Inputs and Outputs
• Inputs are 5V Tolerant
• Latch Feature Hold Inputs to Previous Logic States
• EE Technology
High-
– Reprogrammable
– 100% Tested
performance
EE PLD
• High-reliability CMOS Process
– 20-year Data Retention
– 10,000 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latch-up Immunity
• Commercial and Industrial Temperature Ranges
• Dual Inline and Surface Mount Standard Pinouts
ATF22LV10CZ
ATF22LV10CQZ
Block Diagram
Pin Configurations
TSSOP
All Pinouts Top View
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
2
Pin Name Function
IN
3
IN
4
CLK
IN
Clock
IN
5
IN
6
Logic Inputs
Bi-directional Buffers
Ground
IN
7
IN
8
I/O
IN
9
IN
10
11
12
IN
GND
VCC
GND
(3 to 5.5V) Supply
PLCC
Note:
TSSOP is the smallest package
of SPLD offering.
DIP/SOIC
IN
IN
5
6
7
8
9
25 I/O
24 I/O
23 I/O
22 GND*
21 I/O
20 I/O
19 I/O
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 I/O
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 IN
IN
GND*
IN
IN
IN 10
IN 11
IN
IN
IN
IN
IN
IN
Note:
For PLCC, pins 1, 8, 15, and
22 can be left unconnected.
For superior performance,
connect VCC to pin 1 and
GND to pins 8, 15, and 22.
IN 10
IN 11
Rev. 0779K–04/01
GND 12
1