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ATF22LV10CZ PDF预览

ATF22LV10CZ

更新时间: 2024-11-26 22:50:15
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
9页 226K
描述
High Performance E2 PLD

ATF22LV10CZ 数据手册

 浏览型号ATF22LV10CZ的Datasheet PDF文件第2页浏览型号ATF22LV10CZ的Datasheet PDF文件第3页浏览型号ATF22LV10CZ的Datasheet PDF文件第4页浏览型号ATF22LV10CZ的Datasheet PDF文件第5页浏览型号ATF22LV10CZ的Datasheet PDF文件第6页浏览型号ATF22LV10CZ的Datasheet PDF文件第7页 
Features  
3.0V to 5.5V Operating Range  
Advanced Low Voltage, Zero Power,  
Electrically Erasable Programmable Logic Device  
Edge-Sensing “Zero” Power  
Low Voltage Equivalent of ATF22V10CZ  
“Zero” Standby Power (25 µA Maximum)  
Ideal for Battery Powered Systems  
25 ns Maximum Propagation Delay  
CMOS and TTL Compatible Inputs and Outputs  
High  
Latch Feature Hold Inputs to Previous Logic States  
Advanced E2 Technology  
Performance  
E2 PLD  
Reprogrammable  
100% Tested  
High Reliability CMOS Process  
20 Year Data Retention  
100 Erase/Write Cycles  
2,000V ESD Protection  
200 mA Latchup Immunity  
ATF22LV10CZ  
Commercial and Industrial Temperature Ranges  
Dual-in-Line and Surface Mount Standard Pinouts  
Block Diagram  
ATF22LV10CZ  
TSSOP Top View  
Pin Configurations  
CLK/IN  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
IN  
Pin Name  
CLK  
IN  
Function  
IN  
IN  
2
3
Clock  
IN  
4
IN  
5
Logic Inputs  
Bidirectional Buffers  
(3 to 5.5V) Supply  
IN  
6
IN  
7
I/O  
IN  
8
IN  
9
VCC  
IN  
10  
11  
12  
IN  
GND  
DIP/SOIC  
PLCC  
Top view  
Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For supe-  
rior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22.  
Rev. 0779E/LV10CZ-E–05/98  

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