Features
• User-Controlled Power Down Pin
• High-Speed Equivalent of ATF20V8B
• Pin-Controlled Zero Standby Power (10 µA Typical) Option
• Industry Standard Architecture
– Emulates Many 24-Pin PALs®
– Low-Cost Easy-to-Use Software Tools
• High-Speed Electrically-Erasable Programmable Logic Devices
– 5 ns Maximum Pin-to-Pin Delay
• CMOS and TTL Compatible Inputs and Outputs
– Latch Feature Hold Outputs to Previous Logic States
• Advanced Flash Technology
High-
– Reprogrammable
Performance
EE PLD
– 100% Tested
• High-Reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
ATF20V8C
• Commercial, and Industrial Temperature Ranges
• Dual-in-Line and Surface Mount Packages in Standard Pinouts
• PCI Compliant
Advance
Block Diagram
Information
TSSOP Top View
Pin Configurations
CLK/IN
IN
1
24
23
22
21
20
19
18
17
16
15
14
13
VCC
IN
Pin Name Function
2
IN
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
CLK
IN
Clock
PD/IN
IN
4
5
Logic Inputs
IN
6
IN
7
I/O
OE
*
Bidirectional Buffers
Output Enable
No Internal Connection
+5V Supply
IN
8
IN
9
IN
10
11
12
IN
GND
OE/IN
VCC
PD
Power Down
PLCC Top View
DIP
CLK/IN
IN
1
2
3
4
5
6
7
8
9
24 VCC
23 IN
PD/IN
5
6
7
8
9
25 I/O
24 I/O
23 I/O
IN
IN
*
IN
22 I/O
21 I/O
20 I/O
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 IN
PD/IN
IN
22
*
IN
21 I/O
20 I/O
19 I/O
IN
IN 10
IN 11
IN
IN
IN
Rev. 0408D–01/99
IN 10
IN 11
GND 12
13 OE/IN
1