Datasheet > ATF1516SE-10RI256

ATF1516SE-10RI256

更新时间： 2024-02-22 21:52:29

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟 ATM 异步传输模式输入元件可编程逻辑
页数	文件大小	规格书
60页	1086K
描述
EE PLD, 10ns, PQFP208, HEAT SPREADER, PLASTIC, QFP-208

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技术参数
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ATF1516SE-10RI256 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	HEAT SPREADER, PLASTIC, QFP-208	针数：	208
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	其他特性：	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
最大时钟频率：	125 MHz	JESD-30 代码：	S-PQFP-G208
长度：	28 mm	专用输入次数：
I/O 线路数量：	160	端子数量：	208
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 160 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	FQFP
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
可编程逻辑类型：	EE PLD	传播延迟：	10 ns
认证状态：	Not Qualified	座面最大高度：	3.85 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	28 mm	Base Number Matches：	1

ATF1516SE-10RI256 数据手册

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Power-on Reset

The ATF15xx Family devices are designed with a power-on reset, a feature critical for state

machine initialization. At a point delayed slightly from V_CCcrossing V_RST, all registers will be

initialized, and the state of each output will depend on the polarity of its buffer. However, due

to the asynchronous nature of reset and uncertainty of how V_CCactually rises in the system,

the following conditions are required:

1. The V_CCrise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and,

3. The clock must remain stable during T_D.

The ATF15xx Family has two options for the hysteresis about the reset level, V_RST, Small and

Large. In applications where the supply voltage may drop below 4.0V, Atmel recommends that

during the fitting process users configure the device with the Power-on Reset hysteresis set to

Large to ensure a robust operating environment.

Power Down of

Unused

To conserve power, Atmel fitters automatically power down all unused macrocells.

Macrocells

Input Transition

Detection/

Automatic Power

Down

In addition, the ATF15xxSEL devices contain ITD (Input Transition Detection) Circuits on Glo-

bal Clocks, Inputs and I/O. ITD automatically puts the device into a low-power standby mode

when no logic transitions are occurring. This reduces power consumption during inactive peri-

ods, and therefore also provides proportional power-savings for most applications running at

system speeds below 5 MHz.

Reduced-Power

per Macrocell

To further reduce power, each ATF15xxSE Family macrocell has a reduced-power bit feature.

With this feature the designer can reduce power by 50% or more for logic that does not need

to operate at the maximum switching speed. The reduced-power bit may be activated by

changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power

mode (reduced-power bit turned on), the reduced- power adder, t_RPA, must be added to the

AC parameters, which include the data paths t_LAD, t_LAC, t_IC, t_ACL, t_ACHand t_SEXP. All power-down

AC characteristic parameters are computed from external input or I/O pins, with the reduced-

power bit turned on.

Slew Rate Control

Each output also has individual slew rate control. This may be used to reduce system noise by

slowing down outputs that do not need to operate at maximum speed. Outputs default to slow

switching. The slew rate option is selected in the design source file.

Pin Controlled

Power-down

All ATF15xx Family devices also have an optional pin-controlled power-down mode. When

activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device

goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply

current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as

are any enabled outputs. Therefore, all registered and combinatorial output data remain valid.

Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold

latches remain active to ensure that pins do not float to indeterminate levels, further reducing

system power. All pin transitions are ignored until the PD pin is brought low. When the power-

down feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output.

However, the pin’s macrocell may still be used to generate buried foldback and cascade logic

signals. The power-down option is selected in the design source file.

ATF15xxSE Family

2401A–08/01

1...7 8 91011 12 13...60

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与ATF1516SE-10RI256相关器件

型号	品牌	描述	获取价格	数据表
ATF1516SE-5QC208	ATMEL	EE PLD, 6ns, PQFP208, PLASTIC, QFP-208	获取价格
ATF1516SE-5RC256	ATMEL	EE PLD, 6ns, PQFP208, HEAT SPREADER, PLASTIC, QFP-208	获取价格
ATF1516SE-7QC208	ATMEL	EE PLD, 7.5ns, PQFP208, 28 X 28 MM, PLASTIC, QFP-208	获取价格
ATF1516SE-7QI208	ATMEL	EE PLD, 7.5ns, PQFP208, 28 X 28 MM, PLASTIC, QFP-208	获取价格
ATF1516SE-7RC208	ATMEL	EE PLD, 7.5ns, PQFP208, 28 X 28 MM, PLASTIC, RQFP-208	获取价格
ATF1516SE-7RC256	ATMEL	EE PLD, 7.5ns, PQFP208, HEAT SPREADER, PLASTIC, QFP-208	获取价格

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