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ATF1516ASL-25QC160 PDF预览

ATF1516ASL-25QC160

更新时间： 2024-01-17 11:26:44
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件异步传输模式ATM时钟
页数 文件大小 规格书
11页 269K
描述
High Performance EE-Based CPLD

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ATF1516ASL-25QC160 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, QFP-160
针数：160Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.92
Is Samacsys：N最大时钟频率：70 MHz
JESD-30 代码：S-PQFP-G160长度：28 mm
湿度敏感等级：1端子数量：160
最高工作温度：70 °C最低工作温度：
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：225
可编程逻辑类型：EE PLD传播延迟：25 ns
认证状态：Not Qualified座面最大高度：3.97 mm
标称供电电压：3 V表面贴装：YES
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
Base Number Matches：1

ATF1516ASL-25QC160 数据手册

 浏览型号ATF1516ASL-25QC160的Datasheet PDF文件第5页浏览型号ATF1516ASL-25QC160的Datasheet PDF文件第6页浏览型号ATF1516ASL-25QC160的Datasheet PDF文件第7页浏览型号ATF1516ASL-25QC160的Datasheet PDF文件第9页浏览型号ATF1516ASL-25QC160的Datasheet PDF文件第10页浏览型号ATF1516ASL-25QC160的Datasheet PDF文件第11页 
JTAG-BST Overview  
The JTAG boundary-scan testing is controlled by the Test  
Access Port (TAP) controller in the ATF1516AS. The  
boundary-scan technique involves the inclusion of a shift-  
register stage (contained in a boundary-scan cell) adjacent  
to each component so that signals at component bound-  
aries can be controlled and observed using scan testing  
principles. Each input pin and I/O pin has its own boundary  
scan cell (BSC) in order to support boundary scan testing.  
The ATF1516AS does not currently include a Test Reset  
(TRST) input pin because the TAP controller is automati-  
cally reset at power up. The six JTAG BST modes sup-  
ported include: SAMPLE/PRELOAD, EXTEST, BYPASS,  
IDCODE. BST on the ATF1516AS is implemented using  
the Boundary Scan Definition Language (BSDL) described  
in the JTAG specification (IEEE Standard 1149.1). Any  
third party tool that supports the BSDL format can be used  
to perform BST on the ATF1516AS.  
BSC Configuration Pins and  
Macrocells (except JTAG TAP Pins)  
Note:  
The ATF1516AS has pull-up option on TMS and TDI  
pins. This feature is selected as a design option.  
The ATF1516AS also has the option of using four JTAG-  
standard I/O pins for in-system programming (ISP). The  
ATF1516AS is programmable through the four JTAG pins  
using programming compatible with the IEEE JTAG Stan-  
dard 1149.1. Programming is performed by using 5V TTL-  
level programming signals from the JTAG ISP interface.  
The JTAG feature is a programmable option. If JTAG (BST  
or ISP) is not needed, then the four JTAG control pins are  
available as I/O pins.  
JTAG Boundary Scan Cell (BSC)  
Testing  
The ATF1516AS contains up to 160 I/O pins and 4 input  
pins, depending on the device type and package type  
selected. Each input pin and I/O pin has its own boundary  
scan cell (BSC) in order to support boundary scan testing  
as described in detail by IEEE Standard 1149.1. Typical  
BSC consists of three capture registers or scan registers  
and up to two update registers. There are two types of  
BSCs, one for input or I/O pin, and one for the macrocells.  
The BSCs in the device are chained together through the  
capture registers. Input to the capture register chain is fed  
in from the TDI pin while the output is directed to the TDO  
pin. Capture registers are used to capture active device  
data signals, to shift data in and out of the device and to  
load data into the update registers. Control signals are gen-  
erated internally by the JTAG TAP controller. The BSC  
configuration for the input and I/O pins and macrocells are  
shown below.  
ATF1516AS/L  
8
1...567891011

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