ATF1516ASL-25QC160

更新时间： 2024-01-29 14:17:18

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件异步传输模式 ATM 时钟
页数	文件大小	规格书
11页	269K
描述
High Performance EE-Based CPLD

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ATF1516ASL-25QC160 技术参数

ATF1516AS/L

Input Test Waveforms and

Measurement Levels

Output AC Test Loads:

(3.0V)*

(703 )*

(8060 )*

Note:

*Numbers in parenthesis refer to 3.0V operating condi-

tions (preliminary).

r_R, t_F= 1.5 ns typical

Power Down Mode

The ATF1516AS includes two pins for optional pin con-

trolled power down feature. When this mode is enabled, the

PD pin acts as the power down pin. When the PD1 and

PD2 pin is high, the device supply current is reduced to

less than 3 mA. During power down, all output data and

internal logic states are latched and held. Therefore, all

registered and combinatorial output data remain valid. Any

outputs which were in a Hi-Z state at the onset will remain

at Hi-Z. During power down, all input signals except the

power down pin are blocked. Input and I/O hold latches

remain active to insure that pins do not float to indetermi-

nate levels, further reducing system power. The power

down pin feature is enabled in the logic design file. Designs

using either power down pin may not use the PD pin logic

array input. However, all other PD pin as macrocell

resources may still be used, including the buried feedback

and foldback product term array inputs.

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