Datasheet > ATF1508SE-10AC100

ATF1508SE-10AC100

更新时间： 2024-01-07 10:52:59

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟输入元件可编程逻辑
页数	文件大小	规格书
69页	596K
描述
EE PLD, 10ns, 128-Cell, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100

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ATF1508SE-10AC100 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TFQFP, TQFP100,.63SQ
针数：	100	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.8
其他特性：	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V	最大时钟频率：	125 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQFP-G100
JESD-609代码：	e0	JTAG BST：	YES
长度：	14 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	80
宏单元数：	128	端子数量：	100
最高工作温度：	70 °C	最低工作温度：
组织：	0 DEDICATED INPUTS, 80 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TFQFP
封装等效代码：	TQFP100,.63SQ	封装形状：	SQUARE
封装形式：	FLATPACK, THIN PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	240
电源：	3.3/5,5 V	可编程逻辑类型：	EE PLD
传播延迟：	10 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

ATF1508SE-10AC100 数据手册

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ATF15xxSE Family

Functional

Description

The ATF15xxSE Family of 5.0 Volt supply, high-performance, high-density complex program-

mable logic devices (CPLDs) utilizes Atmel’s proven electrically erasable non-volatile

technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI,

LSI and classic PLDs. The ATF15xxSE Family’s enhanced macrocell architecture, switch

matrices and routing increase usable gate count for new designs and increase odds of suc-

cessful pin-locked design modifications while maintaining pin-compatibility with industry

standard CPLDs.

The ATF15xxSE Family devices have four dedicated input pins and depending on the type of

device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve

as a global control signal, register clock, register reset or output enable. Each of these control

signals can be selected for use individually within each macrocell. Each input and I/O pin also

feeds into the global bus.

The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in

each logic block selects 40 individual signals from the global bus. Macrocells within a given

logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic

between macrocells in the Logic Block allows fast, efficient generation of complex logic func-

tions. All macrocells are capable of being I/Os, however, the actual number of I/O pins

depends on the device and package type. The ATF15xxSE Family members contain two, four,

eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a

fan-in of 40 inputs from the switch matrix having access to up to 80 product terms.

Unused macrocells are automatically disabled by the fitter software to decrease power con-

sumption. A security fuse, when programmed, protects the contents of the other fuses. Two

bytes (16 bits) of User Signature are accessible to the user for purposes such as storing

project name, part number, revision or date. The User Signature is accessible regardless of

the state of the security fuse.

The ATF15xxSE Family devices are in-system programmable (ISP) devices. They use the

industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with

JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-

grammed without removing it from the printed circuit board. In addition to simplifying the

manufacturing flow, ISP also allows design modifications to be made in the field via software.

Global Bus/Switch

Matrix

The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback

signals from all macrocells. The switch matrix in each logic block receives as its inputs all sig-

nals from the global bus. Up to 40 of these signals can be selected as inputs to the individual

logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch

matrix signal distribution structure, where each logic block input has access to the same num-

ber of global bus inputs, maximizing the number of possible ways to route a global bus signal.

This single level structure is in contrast with split switch matrix structures used by others in

which routing a particular global bus input to a particular logic block input makes that signal

unavailable to some other logic blocks, thus greatly limiting the available opportunities to

route.

The ATF15xxSE Family macrocell, shown in Figure 2, consists of five sections: product terms

and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and

output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can

generate a foldback logic term from the product term mux and a buried feedback with extra

routing that go to the global bus.

2401D–PLD–09/02

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与ATF1508SE-10AC100相关器件

型号	品牌	描述	获取价格	数据表
ATF1508SE-10AI100	ATMEL	EE PLD, 10ns, 128-Cell, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100	获取价格
ATF1508SE-10JC84	ATMEL	EE PLD, 10ns, 128-Cell, PQCC84, PLASTIC, LCC-84	获取价格
ATF1508SE-10JI84	ATMEL	EE PLD, 10ns, 128-Cell, PQCC84, PLASTIC, LCC-84	获取价格
ATF1508SE-10QC100	ATMEL	EE PLD, 10ns, 128-Cell, PQFP100, 14 X 20 MM, PLASTIC, QFP-100	获取价格
ATF1508SE-10QC160	ATMEL	EE PLD, 10ns, 128-Cell, PQFP160, 28 X 28 MM, PLASTIC, QFP-160	获取价格
ATF1508SE-10QI100	ATMEL	EE PLD, 10ns, 128-Cell, PQFP100, 14 X 20 MM, PLASTIC, QFP-100	获取价格

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