Datasheet > ATF1504SE-6JC44

ATF1504SE-6JC44

更新时间： 2022-12-01 19:40:29

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
69页	601K
描述
EE PLD, 6ns, 64-Cell, CMOS, PQCC44, PLASTIC, LCC-44

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ATF1504SE-6JC44 数据手册

Flip-flop

The ATF15xxSE Family’s flip-flop has very flexible data and control functions. The data input

can come from either the XOR gate, from a separate product term or directly from the I/O pin.

Selecting the separate product term allows creation of a buried registered feedback within a

combinatorial output or vice-versa. (This enhanced function is automatically implemented by

the fitter software). The flip-flop can be configured for D, T, JK and SR operation, and changes

state on the clock’s rising edge. It can also be configured as a flow-through latch. In this mode,

data passes through when the clock is high and is latched when the clock is low.

When a GCK signal is used as the clock, one of the macrocell product terms can be selected

as a clock enable. When the clock enable function is active and the enable signal (product

term) is low, all clock edges are ignored. The flip-flop has asynchronous reset and preset. The

flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product

term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchro-

nous preset (AP) can be a product term or always off.

Extra Feedback

I/O Control

The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The

extra buried feedback signal can be either combinatorial or registered signal regardless of

whether the output is combinatorial or registered. (This enhanced function is automatically

implemented by the fitter software) Feedback of a buried combinatorial output allows the cre-

ation of a second latch within a macrocell.

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be indi-

vidually configured as an input, output or for bi-directional operation. The output enable for

each macrocell can be selected from the true or compliment of the two output enable pins, a

subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done

by the fitter software when the I/O is configured as an input, all macrocell resources are still

available, including the buried feedback, expander and cascade logic.

The buffer has a fast/slow slew rate option to control EMI and an open-collector option which

enables the device to provide control signals such as an interrupt that can be asserted by any

of the several devices.

Programmable

Pin-keeper Option

for Inputs and I/Os

The ATF15xxSE Family offers the option of programming all input and I/O pins with pin-keeper

circuits enabled. When any pin is driven high or low and then subsequently left floating, the pin

keeper circuit will hold it at that previous high or low-level. This circuitry prevents unused input

and I/O lines from floating to intermediate voltage levels, which causes unnecessary power

consumption and system noise. The pin-keeper circuits eliminate the need for external pull-up

resistors and eliminate their DC power consumption.

ATF15xxSE Family

2401D–PLD–09/02

1...3 4 567 8 9...69

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与ATF1504SE-6JC44相关器件

型号	品牌	描述	获取价格	数据表
ATF1504SE-6JC84	ATMEL	EE PLD, 6ns, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84	获取价格
ATF1504SE-7AC100	ATMEL	EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100	获取价格
ATF1504SE-7AC44	ATMEL	EE PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44	获取价格
ATF1504SE-7AI100	ATMEL	EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100	获取价格
ATF1504SE-7AI44	ATMEL	EE PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.8 MM PITCH, PLASTIC, TQFP-44	获取价格
ATF1504SE-7J84	ATMEL	EE PLD, 7.5ns, PQCC84, PLASTIC, LCC-84	获取价格

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