ATF15xxSE Family
Functional
Description
The ATF15xxSE Family of 5.0 Volt supply, high-performance, high-density complex program-
mable logic devices (CPLDs) utilizes Atmel’s proven electrically erasable non-volatile
technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI,
LSI and classic PLDs. The ATF15xxSE Family’s enhanced macrocell architecture, switch
matrices and routing increase usable gate count for new designs and increase odds of suc-
cessful pin-locked design modifications while maintaining pin-compatibility with industry
standard CPLDs.
The ATF15xxSE Family devices have four dedicated input pins and depending on the type of
device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these control
signals can be selected for use individually within each macrocell. Each input and I/O pin also
feeds into the global bus.
The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in
each logic block selects 40 individual signals from the global bus. Macrocells within a given
logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic
between macrocells in the Logic Block allows fast, efficient generation of complex logic func-
tions. All macrocells are capable of being I/Os, however, the actual number of I/O pins
depends on the device and package type. The ATF15xxSE Family members contain two, four,
eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a
fan-in of 40 inputs from the switch matrix having access to up to 80 product terms.
Unused macrocells are automatically disabled by the fitter software to decrease power con-
sumption. A security fuse, when programmed, protects the contents of the other fuses. Two
bytes (16 bits) of User Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Signature is accessible regardless of
the state of the security fuse.
The ATF15xxSE Family devices are in-system programmable (ISP) devices. They use the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-
grammed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via software.
Global Bus/Switch
Matrix
The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback
signals from all macrocells. The switch matrix in each logic block receives as its inputs all sig-
nals from the global bus. Up to 40 of these signals can be selected as inputs to the individual
logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch
matrix signal distribution structure, where each logic block input has access to the same num-
ber of global bus inputs, maximizing the number of possible ways to route a global bus signal.
This single level structure is in contrast with split switch matrix structures used by others in
which routing a particular global bus input to a particular logic block input makes that signal
unavailable to some other logic blocks, thus greatly limiting the available opportunities to
route.
The ATF15xxSE Family macrocell, shown in Figure 2, consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and
output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can
generate a foldback logic term from the product term mux and a buried feedback with extra
routing that go to the global bus.
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2401D–PLD–09/02
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