Datasheet > ATF1504ASVL_14

ATF1504ASVL_14

更新时间： 2022-02-26 12:39:13

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
31页	578K
描述
High-density, High-performance, Electrically-erasable Complex

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ATF1504ASVL_14 数据手册

Input Diagram

I/O Diagram

Speed/Power

Management

The ATF1504ASV(L) has several built-in speed and power management features. The

ATF1504ASV(L) contains circuitry that automatically puts the device into a low power

standby mode when no logic transitions are occurring. This not only reduces power con-

sumption during inactive periods, but also provides proportional power savings for most

applications running at system speeds below 5 MHz. This feature may be selected as a

device option.

To further reduce power, each ATF1504ASV(L) macrocell has a reduced-power bit fea-

ture. This feature allows individual macrocells to be configured for maximum power

savings. This feature may be selected as a design option.

All ATF1504ASV(L) also have an optional power-down mode. In this mode, current

drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins

(or both) can be used to power down the part. The power-down option is selected in the

design source file. When enabled, the device goes into power down when either PD1 or

PD2 is high. In the power-down mode, all internal logic signals are latched and held, as

are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power-down fea-

ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,

the pin’s macrocell may still be used to generate buried foldback and cascade logic

signals.

ATF1504ASV(L)

1409J–PLD–6/05

1...5 6 789 10 11...31

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