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ATF1504ASVL-20AU44 PDF预览

ATF1504ASVL-20AU44

更新时间: 2024-02-14 10:56:58
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
31页 559K
描述
Low-voltage, Complex Programmable Logic Device

ATF1504ASVL-20AU44 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.31.00.01风险等级:5.49
最大时钟频率:83.3 MHzJESD-30 代码:S-PQFP-G44
长度:10 mm专用输入次数:
I/O 线路数量:32端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 32 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:TQFP
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE
可编程逻辑类型:EE PLD传播延迟:20 ns
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

ATF1504ASVL-20AU44 数据手册

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ATF1504ASV(L)  
Block Diagram  
Unused product terms are automatically disabled by the compiler to decrease power  
consumption. A security fuse, when programmed, protects the contents of the  
ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for  
purposes such as storing project name, part number, revision or date. The User Signa-  
ture is accessible regardless of the state of the security fuse.  
The ATF1504ASV(L) device is an in-system programmable (ISP) device. It uses the  
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with  
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-  
grammed without removing it from the printed circuit board. In addition to simplifying the  
manufacturing flow, ISP also allows design modifications to be made in the field via  
software.  
Product Terms and Select  
Mux  
Each ATF1504ASV(L) macrocell has five product terms. Each product term receives as  
its inputs all signals from both the global bus and regional bus.  
The product term select multiplexer (PTMUX) allocates the five product terms as  
needed to the macrocell logic gates and control signals. The PTMUX programming is  
determined by the design compiler, which selects the optimum macrocell configuration.  
5
1409J–PLD–6/05  

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