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ATF1504ASVL-20AU44 PDF预览

ATF1504ASVL-20AU44

更新时间： 2024-02-22 16:31:57
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程逻辑器件
页数 文件大小 规格书
31页 559K
描述
Low-voltage, Complex Programmable Logic Device

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中文翻译

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ATF1504ASVL-20AU44 技术参数

生命周期：Transferred零件包装代码：QFP
包装说明：10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, MS-026ACB, TQFP-44针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.31.00.01风险等级：5.49
最大时钟频率：83.3 MHzJESD-30 代码：S-PQFP-G44
长度：10 mm专用输入次数：
I/O 线路数量：32端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 32 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE
可编程逻辑类型：EE PLD传播延迟：20 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
宽度：10 mmBase Number Matches：1

ATF1504ASVL-20AU44 数据手册

 浏览型号ATF1504ASVL-20AU44的Datasheet PDF文件第5页浏览型号ATF1504ASVL-20AU44的Datasheet PDF文件第6页浏览型号ATF1504ASVL-20AU44的Datasheet PDF文件第7页浏览型号ATF1504ASVL-20AU44的Datasheet PDF文件第9页浏览型号ATF1504ASVL-20AU44的Datasheet PDF文件第10页浏览型号ATF1504ASVL-20AU44的Datasheet PDF文件第11页 
Input Diagram  
I/O Diagram  
Speed/Power  
Management  
The ATF1504ASV(L) has several built-in speed and power management features. The  
ATF1504ASV(L) contains circuitry that automatically puts the device into a low power  
standby mode when no logic transitions are occurring. This not only reduces power con-  
sumption during inactive periods, but also provides proportional power savings for most  
applications running at system speeds below 5 MHz. This feature may be selected as a  
device option.  
To further reduce power, each ATF1504ASV(L) macrocell has a reduced-power bit fea-  
ture. This feature allows individual macrocells to be configured for maximum power  
savings. This feature may be selected as a design option.  
All ATF1504ASV(L) also have an optional power-down mode. In this mode, current  
drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins  
(or both) can be used to power down the part. The power-down option is selected in the  
design source file. When enabled, the device goes into power down when either PD1 or  
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as  
are any enabled outputs.  
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-  
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,  
the pin’s macrocell may still be used to generate buried foldback and cascade logic  
signals.  
8
ATF1504ASV(L)  
1409J–PLD–6/05  
1...567891011...31

中文翻译

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ATF1504ASVL-20AU44 替代型号

型号 品牌 替代类型 描述 数据表
ATF1504ASVL-20AC44 ATMEL

类似代替

 Low-voltage, Complex Programmable Logic Device
ATF1504ASVL-20AI44 ATMEL

类似代替

 Low-voltage, Complex Programmable Logic Device
EPM3064ATC44-10N ALTERA

功能相似

 Programmable Logic Device Family

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