General
Description
Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells
in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability.
Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel
ATF15xx Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling archi-
tecture consists of wider fan-in, additional routing and clock options, combined with
sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel
enhanced macrocell includes double independent buried feedback that allows designers to
pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for
later revisions. The Atmel ATF15xx family delivers enhanced functionality and flexibility with
no additional design effort and is highly cost effective.
The Atmel ATF15xx Family includes all popular configurations and speeds.
Table 1. ATF15xxAE Family Device Features
Feature
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
6000
ATF1532AE(L)
12000
512
Usable Gates
Macrocells
750
1500
3000
128
32
64
256
Logic Blocks
Max. # Pins
Max. User I/Os
TPD Grades (ns)
2
44
4
100
8
16
32
256
256
256
36
68
100
164
212
4, 7, 10(15)
4, 7, 10(15)
5, 7, 10(15)
5, 7, 10(15)
5, 7, 12(15)
The Atmel ATF15xxAE Family includes pin-compatible products in all popular packages.
Table 2. ATF15xxAE Family Device Packages and Number of Signal Pins(1)(2)
Packages
ATF1502AE(L)
ATF1504AE(L)
ATF1508AE(L)
ATF1516AE(L)
ATF1532AE(L)
44-pin PLCC
44-pin TQFP
49-ball BGA
84-pin PLCC
100-pin TQFP
100-ball BGA
144-pin TQFP
169-ball BGA
208-pin PQFP
256-ball BGA
36
36
36
36
41
68
84
68
68
84
84
84
100
100
120
120
164
164
176
212
100
Notes: 1. Contact Atmel for up-to-date information on device and package availability.
2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing
(BST), the four associated pins become JTAG pins and are unavailable for user I/O.
2
ATF15xxAE Family
2398E–12/01