Datasheet > ATF1502AS_05

ATF1502AS_05

更新时间： 2022-12-27 23:40:31

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
26页	517K
描述
Highperformance EEPROM CPLD

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数据手册

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ATF1502AS_05 数据手册

ATF1502AS(L)

JTAG

The ATF1502AS contains up to 32 I/O pins and four input pins, depending on the device type

and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC)

in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A

typical BSC consists of three capture registers or scan registers and up to two update regis-

ters. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The

BSCs in the device are chained together through the capture registers. Input to the capture

registers are used to capture active device data signals, to shift data in and out of the device

and to load data into the update registers. Control signals are generated internally by the

JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is

shown below.

Boundary-scan

Cell (BSC)

Testing

BSC

Configuration

for Input and I/O

Pins (Except

JTAG TAP Pins)

Note:

1. The ATF1502AS has a pull-up option on TMS and TDI pins. This feature is selected as a

design option.

BSC

Configuration

for Macrocell

TDO

TDI

CLOCK

TDO

OEJ

D Q

OUTJ

D Q

Capture

Update

Mode

TDI

Clock

Shift

BSC for I/O Pins and Macrocells

0995K–PLD–6/05

1...6 7 8910 11 12...26

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