Datasheet > ATA6565

ATA6565

更新时间： 2023-12-06 20:09:35

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
32页	1242K
描述
The Microchip ATA6565 is a fully integrated dual high-speed CAN transceiver with two completely in

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ATA6565 数据手册

ATA6565

The wake-up pattern consists of at least two consecu-

1.1.2

STANDBY MODE

tive dominant bus levels for a duration of at least t_Filter

A high level on the STBY pin selects Standby mode. In

this mode, the transceiver is not able to transmit or

correctly receive data via the bus lines. The transmitter

and the HSC are switched off to reduce current con-

sumption.

each separated by a recessive bus level with a duration

of at least t_Filter. Dominant or recessive bus levels

shorter than t_Filterare always ignored. The complete

dominant-recessive-dominant pattern, as shown in

Figure 1-3, must be received within the bus wake-up

time-out time, t_Wake, to be recognized as a valid

wake-up pattern. Otherwise, the internal wake-up logic

is reset and then the complete wake-up pattern must

be retransmitted to trigger a wake-up event. The RXD

pin remains at a high level until a valid wake-up event

has been detected.

1.1.2.1

Remote Wake-Up via CAN Bus

In Standby mode, the bus lines are biased to ground to

reduce current consumption to a minimum. The device

monitors the bus lines for a valid wake-up pattern, as

specified in the ISO 11898-2:2016. This filtering helps

to avoid spurious wake-up events that would be

triggered by scenarios, such as a dominant clamped

bus or a dominant phase due to noise, spikes on the

bus, automotive transients, or EMI.

During Normal mode, at a VCC undervoltage condition

or when the complete wake-up pattern is not received

within t_Wake, no wake-up is signaled at the RXD pin.

FIGURE 1-3:

TIMING OF BUS WAKE-UP PATTERN (WUP) IN STANDBY MODE

CANH

CANL

dominant

recessive

dominant

V_Diff

t_dom= t_)LOWHU

t_rec= t_)LOWHU

t_dom= t_)LOWHU

WꢀꢀW_:DNH

RXD

Bus Wake-up

is Signaled

When a valid CAN wake-up pattern is detected on the

bus, the RXD pin switches to low to signal a wake-up

request. A transition to Normal mode is not triggered

until the STBY pin is forced back to low by the

microcontroller.

failure from driving the bus lines to a permanent domi-

nant state (blocking all network communications). The

TXD dominant time-out timer is reset when the TXD pin

is set to high. If the low state on the TXD pin is longer

than t_to(dom)TXD, then the TXD pin has to be set to high

≥ 4 µs in order to reset the TXD dominant time-out timer.

1.2

Fail-Safe Features

1.2.2

INTERNAL PULL-UP STRUCTURE

AT TXD AND STBY INPUT PINS

1.2.1

TXD DOMINANT TIME-OUT

FUNCTION

The TXD and STBY pins have an internal pull-up to

VCC. This ensures a safe, defined state in case one or

both pins are left floating. Pull-up currents flow in these

pins in all states, meaning all pins should be in a high

state during Standby mode to minimize the current

consumption.

A TXD dominant time-out timer is started when the TXD

pin is set to low. If the low state on the TXD pin persists

for longer than t_to(dom)TXD, the transmitter is disabled,

releasing the bus lines to the recessive state. This func-

tion prevents a hardware and/or software application

 2017-2020 Microchip Technology Inc.

DS20005782E-page 5

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