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ATA6020N-XXX-TKQ

更新时间： 2024-02-15 09:15:31
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
66页 867K
描述
Microcontroller, 4-Bit, MROM, MARC4 CPU, 4MHz, CMOS, PDSO20,

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ATA6020N-XXX-TKQ 技术参数

生命周期：Active包装说明：4.40 MM, LEAD FREE, SSOP-20
Reach Compliance Code：compliant风险等级：5.76
具有ADC：NO地址总线宽度：
位大小：4最大时钟频率：8 MHz
DAC 通道：NODMA 通道：NO
外部数据总线宽度：JESD-30 代码：R-PDSO-G20
长度：6.5 mmI/O 线路数量：12
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °CPWM 通道：YES
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
ROM可编程性：MROM座面最大高度：1.1 mm
最大供电电压：6.5 V最小供电电压：2.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
uPs/uCs/外围集成电路类型：MICROCONTROLLERBase Number Matches：1

ATA6020N-XXX-TKQ 数据手册

 浏览型号ATA6020N-XXX-TKQ的Datasheet PDF文件第4页浏览型号ATA6020N-XXX-TKQ的Datasheet PDF文件第5页浏览型号ATA6020N-XXX-TKQ的Datasheet PDF文件第6页浏览型号ATA6020N-XXX-TKQ的Datasheet PDF文件第8页浏览型号ATA6020N-XXX-TKQ的Datasheet PDF文件第9页浏览型号ATA6020N-XXX-TKQ的Datasheet PDF文件第10页 
ATA6020N  
ALU  
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top  
two elements of the expression stack (TOS and TOS-1) and returns the result to the  
TOS. The ALU operations affects the carry/borrow and branch flag in the condition code  
register (CCR).  
Figure 7. ALU Zero-address Operations  
RAM  
TOS-1  
TOS-2  
TOS-3  
TOS-4  
SP  
TOS  
ALU  
CCR  
I/O Bus  
The I/O ports and the registers of the peripheral modules are I/O mapped. All communi-  
cation between the core and the on-chip peripherals take place via the I/O bus and the  
associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a  
direct read or write access to one of the 16 primary I/O addresses. More about the I/O  
access to the on-chip peripherals is described in the section “Peripheral Modules”. The  
I/O bus is internal and is not accessible by the customer on the final microcontroller  
device, but it is used as the interface for the MARC4 emulation (see section  
“Emulation”).  
Instruction Set  
The MARC4 instruction set is optimized for the high level programming language  
qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to  
generate a fast and compact program code. The CPU has an instruction pipeline allow-  
ing the controller to prefetch an instruction from ROM at the same time as the present  
instruction is being executed. The MARC4 is a zero address machine, the instructions  
containing only the operation to be performed and no source or destination address  
fields. The operations are implicitly performed on the data placed on the stack. There  
are one- and two-byte instructions which are executed within 1 to 4 machine cycles. A  
MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the  
instructions are only one byte long and are executed in a single machine cycle. For  
more information refer to the “MARC4 Programmer’s Guide”.  
Interrupt Structure  
The MARC4 can handle interrupts with eight different priority levels. They can be gener-  
ated from the internal and external interrupt sources or by a software interrupt from the  
CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the  
service routine in ROM (see Table 1 on page 9). The programmer can postpone the pro-  
cessing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt  
occurrence will still be registered, but the interrupt routine only starts after the I-flag is  
set. All interrupts can be masked, and the priority individually software configured by  
programming the appropriate control register of the interrupting module (see section  
“Peripheral Modules”).  
7
4708C–4BMCU–02/04  
1...45678910...66

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与ATA6020N-XXX-TKQ相关器件

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ATA6020N-XXX-TKS ATMEL Microcontroller, 4-Bit, MROM, MARC4 CPU, 4MHz, CMOS, PDSO20,

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ATA6020N-YYY-TKQ ATMEL Microcontroller, 4-Bit, MROM, 4MHz, CMOS, PDSO20, SSOP-20

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ATA6020N-YYY-TKQY ATMEL 暂无描述

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