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ATA6020N-XXX-TKQ PDF预览

ATA6020N-XXX-TKQ

更新时间: 2024-02-17 22:00:17
品牌 Logo 应用领域
爱特美尔 - ATMEL 微控制器
页数 文件大小 规格书
66页 867K
描述
Microcontroller, 4-Bit, MROM, MARC4 CPU, 4MHz, CMOS, PDSO20,

ATA6020N-XXX-TKQ 技术参数

生命周期:Active包装说明:4.40 MM, LEAD FREE, SSOP-20
Reach Compliance Code:compliant风险等级:5.76
具有ADC:NO地址总线宽度:
位大小:4最大时钟频率:8 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:R-PDSO-G20
长度:6.5 mmI/O 线路数量:12
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
ROM可编程性:MROM座面最大高度:1.1 mm
最大供电电压:6.5 V最小供电电压:2.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

ATA6020N-XXX-TKQ 数据手册

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RAM Address Registers  
The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y.  
These registers allow access to any of the 256 RAM nibbles.  
Expression Stack Pointer (SP)  
The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the  
expression stack. The pointer is automatically pre-incremented if a nibble is moved onto  
the stack or post-decremented if a nibble is removed from the stack. Every post-decre-  
ment operation moves the item (TOS-1) to the TOS register before the SP is  
decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate  
the start address of the expression stack area.  
Return Stack Pointer (RP)  
The return stack pointer points to the top element of the 12-bit wide return stack. The  
pointer automatically pre-increments if an element is moved onto the stack, or it post-  
decrements if an element is removed from the stack. The return stack pointer incre-  
ments and decrements in steps of 4. This means that every time a 12-bit element is  
stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH  
compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initial-  
ized via >RP FCh.  
RAM Address Registers  
(X and Y)  
The X and Y registers are used to address any 4-bit item in RAM. A fetch operation  
moves the addressed nibble onto the TOS. A store operation moves the TOS to the  
addressed RAM location. By using either the pre-increment or post-decrement address-  
ing mode arrays in RAM can be compared, filled or moved.  
Top of Stack (TOS)  
The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory  
reference and I/O operations use this register. The TOS register receives data from the  
ALU, ROM, RAM or I/O bus.  
Condition Code Register (CCR) The 4-bit wide condition code register contains the branch, the carry and the interrupt  
enable flag. These bits indicate the current state of the CPU. The CCR flags are set or  
reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow  
direct manipulation of the condition code register.  
Carry/Borrow (C)  
The carry/borrow flag indicates that the borrowing or carrying out of the arithmetic logic  
unit (ALU) occurred during the last arithmetic operation. During shift and rotate opera-  
tions, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag.  
Branch (B)  
The branch flag controls the conditional program branching. Should the branch flag has  
been set by a previous instruction a conditional branch will cause a jump. This flag is  
affected by arithmetic, logic, shift, and rotate operations.  
Interrupt Enable (I)  
The interrupt enable flag globally enables or disables the triggering of all interrupt rou-  
tines with the exception of the non-maskable reset. After a reset or on executing the DI  
instruction, the interrupt enable flag is reset thus disabling all interrupts. The core will not  
accept any further interrupt requests until the interrupt enable flag has been set again by  
either executing an EI or SLEEP instruction.  
6
ATA6020N  
4708C–4BMCU–02/04  

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