Datasheet > 可编程逻辑 > 现场可编程门阵列> AT94S40AL-25DGL

AT94S40AL-25DGL

更新时间： 2024-02-28 18:31:40

品牌	Logo	应用领域
爱特美尔 - ATMEL		存储微控制器静态存储器栅可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
31页	268K
描述
Field Programmable Gate Array, 2304 CLBs, 40000 Gates, CMOS, PBGA256, 17 X 17 MM, CABGA-256

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中文翻译

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技术参数
数据手册

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AT94S40AL-25DGL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	BGA
包装说明：	LBGA,	针数：	256
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.33	Is Samacsys：	N
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e1
长度：	17 mm	可配置逻辑块数量：	2304
等效关口数量：	40000	端子数量：	256
最高工作温度：	70 °C	最低工作温度：
组织：	2304 CLBS, 40000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	260
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.5 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	TIN SILVER COPPER
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	40
宽度：	17 mm	Base Number Matches：	1

AT94S40AL-25DGL 数据手册

Features

• Multichip Module Containing Field Programmable System Level Integrated Circuit

(FPSLIC^™) and Secure Configuration EEPROM Memory

• 512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System

Programming (ISP)

• Field Programmable System Level Integrated Circuit (FPSLIC)

– AT40K SRAM-based FPGA with Embedded High-performance RISC AVR^®Core and

Extensive Data and Instruction SRAM

• 5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM^™

– 2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM

– High-performance DSP Optimized FPGA Core Cell

– Dynamically Reconfigurable In-System – FPGA Configuration Access Available

On-chip from AVR Microcontroller Core to Support Cache Logic^®Designs

– Very Low Static and Dynamic Power Consumption – Ideal for Portable and

Handheld Applications

Secure

5K - 40K Gates

of AT40K FPGA

with 8-bit

Microcontroller,

up to 36 Kbytes

of SRAM and

On-chip

• Patented AVR Enhanced RISC Architecture

– 120+ Powerful Instructions – Most Single Clock Cycle Execution

– High-performance Hardware Multiplier for DSP-based Systems

– Approaching 1 MIPS per MHz Performance

– C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers

– Low-power Idle, Power-save, and Power-down Modes

– 100 µA Standby and Typical 2-3 mA per MHz Active

• Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM

– Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM

– Up to 16 Kbytes x 8 Internal 15 ns Data SRAM

• JTAG (IEEE Std. 1149.1 Compliant) Interface

– Extensive On-chip Debugging Support

– Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)

• AVR Fixed Peripherals

– Industry-standard 2-wire Serial Interface

Program

Storage

– Two Programmable Serial UARTs

– Two 8-bit Timer/Counters with Separate Prescaler and PWM

– One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture

Modes and Dual 8-, 9- or 10-bit PWM

• Support for FPGA Custom Peripherals

EEPROM

– AVR Peripheral Control – Up to 16 Decoded AVR Address Lines Directly

Accessible to FPGA

– FPGA Macro Library of Custom Peripherals

• Up to 16 FPGA Supplied Internal Interrupts to AVR

• Up to Four External Interrupts to AVR

• 8 Global FPGA Clocks

AT94S

Secure Series

Programmable

SLI

– Two FPGA Clocks Driven from AVR Logic

– FPGA Global Clock Access Available from FPGA Core

• Multiple Oscillator Circuits

– Programmable Watchdog Timer with On-chip Oscillator

– Oscillator to AVR Internal Clock Circuit

– Software-selectable Clock Frequency

– Oscillator to Timer/Counter for Real-time Clock

• V_CC: 3.0V - 3.6V

• 5V Tolerant I/O

• 3.3V 33 MHz PCI Compliant FPGA I/O

– 20 mA Sink/Source High-performance I/O Structures

– All FPGA I/O Individually Programmable

• High-performance, Low-power 0.35µ CMOS Five-layer Metal Process

• State-of-the-art Integrated PC-based Software Suite including Co-verification

Rev. 2314D–FPSLI–2/04

12 3 4 5 6 7...31

中文翻译

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