Datasheet > AT89C51RD2_14

AT89C51RD2_14

更新时间： 2024-11-28 01:21:43

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
4页	55K
描述
During UART Reception, Clearing REN May Generate Unexpected IT

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AT89C51RD2_14 数据手册

Active Errata List

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During UART Reception, Clearing REN May Generate Unexpected IT

Timer 2 – Baud Rate Generator – Long Start Time

C51 Core – Bad Exit of Power-down in X2 Mode

Incorrect Behavior with CPU X2 Mode Bit of HSB

Extra Interrupt

PCA

Timer0/1

–

Boot process - Upper 2Kbytes execution with BLJB=0

Flash/EEPROM - First Read after Load Disturbed

Errata History

80C51 MCUs

Lot Number

Errata List

All

1, 2, 3, 4, 5, 6, 7

AT89C51RD2

AT89C51ED2

Errata Descriptions

1. During UART Reception, Clearing REN May Generate Unexpected IT

During UART reception, if the REN bit is cleared between start bit detection and

the end of reception, the UART will not discard the data (RI is set).

Errata Sheet

Workaround

Test REN at the beginning of Interrupt routine directly after CLR RI, and run the

Interrupt routine code only if REN is set.

2. Timer 2 – Baud Rate Generator

– Long Start Time

When Timer 2 is used as a baud rate generator, TH2 is not loaded with RCAP2H

at the beginning, then UART is not operational before 10,000 machine cycles.

Workaround

Add the initialization of TH2 and TL2 in the initialization of Timer 2.

3. C51 Core

– Bad Exit of Power-down in X2 Mode

When exiting power-down mode by interrupt while CPU is in X2 mode, it leads to

bad execution of the first instruction run when CPU restarts.

Workaround

Set the CPU in X1 mode diretly before entering power-down mode.

4. PCA

– Incorrect behavior with CPU X2 mode bit of HSB

When starting the microcontroller in X2 mode upon reset with the X2 fuse bit of

the HSB, the PCA may not work properly when configured with Timer 0 in X1

mode as clock input.

Workaround

Set the CPU in X2 mode by software by writing CKCON register at the begin of

the application.

5. Timer0/1

– Extra Interrupt

When Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra inter-

rupt may randomly occur for Timer0 or Timer1.

Workaround

4257E–8051–08/07

12 3 4

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