Datasheet > AT88SC3216C_09

AT88SC3216C_09

更新时间： 2022-12-27 23:35:04

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
21页	203K
描述
CryptoMemory 32 Kbit

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AT88SC3216C_09 数据手册

Table 3.

AC Characteristics

Applicable over recommended operating range from V_CC= +2.7 to 5.5V, T_AC= -40°C to +85°C, CL = 30pF

(unless otherwise noted)

Symbol

f_CLK

Parameter

Async Clock Frequency (V_CCRange: +4.5 - 5.5V)

Async Clock Frequency (V_CCRange: +2.7 - 3.3V)

Synch Clock Frequency

Clock Duty cycle

Min

Max

Units

MHZ

f_CLK

t_R

Rise Time - I/O, RST

μS

t_F

Fall Time - I/O, RST

μS

t_R

Rise Time - CLK

9% x period

μS

t_F

Fall Time - CLK

μS

t_AA

Clock Low to Data Out Valid

Start Hold Time

t_HD.STA

t_SU.STA

t_HD.DAT

t_SU.DAT

t_SU.STO

t_DH

200

Start Set-up Time

Data In Hold Time

Data In Set-up Time

100

200

Stop Set-up Time

Data Out Hold Time

Write Cycle Time (at 25° C)

t_WR

Write Cycle Time (-40° to +85°C)

Device Operation for Synchronous Protocols

CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin

may change only during SCL low time periods (see Figure 5 on page 8). Data changes

during SCL high periods will indicate a start or stop condition as defined below.

START CONDITION:

STOP CONDITION:

ACKNOWLEDGE:

A high-to-low transition of SDA with SCL high is a start condition which must precede any

other command (see Figure 6 on page 8).

A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the

stop command will place the EEPROM in a standby power mode (see Figure 6 on page 8).

All addresses and data words are serially transmitted to and from the EEPROM in 8-bit

words. The EEPROM sends a zero to acknowledge that it has received each word. This

happens during the ninth clock cycle.

MEMORY RESET:

After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by

following these steps:

1. Clock up to 9 cycles.

AT88SC3216C

5014KS–SMEM–08/09

1...3 4 567 8 9...21

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