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AT45CS1282 PDF预览

AT45CS1282

更新时间: 2024-11-28 22:39:15
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
33页 249K
描述
128-megabit 2.7-volt Dual-interface Code Shadow DataFlash

AT45CS1282 数据手册

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Features  
Single 2.7V - 3.6V Supply  
Dual-interface Architecture  
– RapidSSerial Interface: 50 MHz Maximum Clock Frequency  
(SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz)  
– Rapid88-bit Interface: 20 MHz Maximum Clock Frequency  
Page Program  
– 16,384 Pages (1,056 Bytes/Page) Main Memory  
Sector Erase Architecture  
– Sixty-three 270,336-byte Sectors  
– One 261,888-byte Sector  
– One 8,488-byte Sector  
128-megabit  
2.7-volt  
Dual-interface  
Code Shadow  
DataFlash®  
Two 1056-byte SRAM Data Buffers – Allows Receiving of Data  
while Reprogramming the Flash Array  
Continuous Read Capability through Entire Array  
– Ideal for Code Shadowing Applications  
Low-power Dissipation  
– 10 mA Active Read Current Typical – Serial Interface  
– 12 mA Active Read Current Typical – 8-bit Interface  
– 15 µA CMOS Standby Current Typical  
Hardware Data Protection  
Security: 128-byte Security Register  
– 64-byte User Programmable Space  
– Unique 64-byte Device Identifier  
JEDEC Standard Manufacturer and Device ID Read  
100 Program/Erase Cycles Per Sector Minimum  
Data Retention – 10 Years  
AT45CS1282  
Preliminary  
Commercial Temperature Range  
Description  
The AT45CS1282 is a 2.7-volt, dual-interface sequential access Flash memory  
ideally suited for infrequent code shadowing applications. This device utilizes Atmel’s  
e-STACMulti-Level Cell (MLC) memory technology, which allows a single cell to  
TSOP Top View: Type 1  
Pin Configurations  
NC  
NC  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
NC  
2
NC  
RDY/BUSY  
RESET  
WP  
3
NC  
Pin Name  
Function  
4
NC  
5
NC  
NC  
6
I/O7*  
I/O6*  
I/O5*  
I/O4*  
VCCP*  
GNDP*  
I/O3*  
I/O2*  
I/O1*  
I/O0*  
SER/BYTE*  
CLK  
NC  
7
CS  
Chip Select  
NC  
8
VCC  
GND  
NC  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
SCK/CLK  
SI  
Serial Clock/Clock  
Serial Input  
NC  
NC  
NC  
CS  
SCK  
SI*  
SO*  
NC  
SO  
Serial Output  
8-bit Input/Output  
NC  
NC  
NC  
NC  
I/O7 - I/O0  
CBGA Top View  
Hardware Page Write  
Protect Pin  
1
2
3
4
5
WP  
A
B
C
D
E
F
RESET  
Chip Reset  
Ready/Busy  
RDY/BUSY  
NC SER/BYTE NC  
I/O2 SCK/CLK GND  
I/O7  
I/O6  
VCC I/O5  
CS RDY/BUSY WP  
I/O4  
Serial/8-bit Interface  
Control  
I/O1  
I/O0  
SER/BYTE  
SO  
SI  
RESET I/O3  
G
H
J
NC GNDP VCCP  
NC  
NC  
Note:  
*Optional Use – See pin description text  
for connection information.  
Rev. 3447A–DFLSH–2/04  

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