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AT28HC64B-90SJ PDF预览

AT28HC64B-90SJ

更新时间: 2024-11-17 03:20:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
18页 323K
描述
EEPROM, 8KX8, 90ns, Parallel, CMOS, PDSO28, 0.300 INCH, PLASTIC, MS-013, SOIC-28

AT28HC64B-90SJ 数据手册

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Features  
Fast Read Access Time – 70 ns  
Automatic Page Write Operation  
– Internal Address and Data Latches for 64 Bytes  
Fast Write Cycle Times  
– Page Write Cycle Time: 10 ms Maximum (Standard)  
2 ms Maximum (Option – Ref. AT28HC64BF Datasheet)  
– 1 to 64-byte Page Write Operation  
Low Power Dissipation  
64K (8K x 8)  
High Speed  
Parallel  
– 40 mA Active Current  
– 100 µA CMOS Standby Current  
Hardware and Software Data Protection  
DATA Polling and Toggle Bit for End of Write Detection  
High Reliability CMOS Technology  
– Endurance: 100,000 Cycles  
EEPROM with  
Page Write and  
Software Data  
Protection  
– Data Retention: 10 Years  
Single 5 V ±10% Supply  
CMOS and TTL Compatible Inputs and Outputs  
JEDEC Approved Byte-wide Pinout  
Industrial Temperature Ranges  
Green (Pb/Halide-free) Packaging Option  
1. Description  
AT28HC64B  
The AT28HC64B is a high-performance electrically-erasable and programmable read-  
only memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits.  
Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers  
access times to 55 ns with power dissipation of just 220 mW. When the device is  
deselected, the CMOS standby current is less than 100 µA.  
The AT28HC64B is accessed like a Static RAM for the read or write cycle without the  
need for external components. The device contains a 64-byte page register to allow  
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to  
64 bytes of data are internally latched, freeing the address and data bus for other  
operations. Following the initiation of a write cycle, the device will automatically write  
the latched data using an internal control timer. The end of a write cycle can be  
detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a  
new access for a read or write can begin.  
Atmel’s AT28HC64B has additional features to ensure high quality and manufactura-  
bility. The device utilizes internal error correction for extended endurance and  
improved data retention characteristics. An optional software data protection mecha-  
nism is available to guard against inadvertent writes. The device also includes an  
extra 64 bytes of EEPROM for device identification or tracking.  
0274K–PEEPR–8/08  

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