AT25128/256
Functional Description
The AT25128/256 is designed to interface directly with the
synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.
Table 3. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is READY.
Bit 0 = 1 indicates the write cycle is in progress.
The AT25128/256 utilizes an 8-bit instruction register. The
list of instructions and their operation codes are contained
in Table 1. All instructions, addresses, and data are trans-
ferred with the MSB first and start with a high-to-low CS
transition..
Bit 1 (WEN)
Bit 1= 0 indicates the device is not WRITE
ENABLED. Bit 1 = 1 indicates the device is
WRITE ENABLED.
Table 1. Instruction Set for the AT25128/256
Bit 2 (BP0)
Bit 3 (BP1)
See Table 4.
See Table 4.
Instruction
Name
Instruction
Format
Operation
Bits 4-6 are 0s when device is not in an internal write cycle.
WREN
WRDI
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
0000 X010
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
Bit 7
(WPEN)
See Table 5.
RDSR
WRSR
READ
WRITE
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruc-
tion allows the user to select one of four levels of protec-
tion. The AT25128/256 is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory seg-
ments can be protected. Any of the data within any
selected segment will therefore be READ only. The block
write protection levels and corresponding status register
control bits are shown in Table 4.
WRITE ENABLE (WREN): The device will power up in the
write disable state when VCC is applied. All programming
instructions must therefore be preceded by a Write Enable
instruction.
The three bits, BP0, BP1, and WPEN are nonvolatile cells
that have the same properties and functions as the regular
memory cells (e.g. WREN, tWC, RDSR).
WRITE DISABLE (WRDI): To protect the device against
inadvertent writes, the Write Disable instruction disables all
programming modes. The WRDI instruction is independent
of the status of the WP pin.
Table 4. Block Write Protect Bits
READ STATUS REGISTER (RDSR): The Read Status
Register instruction provides access to the status register.
The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the
Block Write Protection bits indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion.
Array Addresses
Status Register Bits
Protected
Level
0
BP1
BP0
AT25128
None
AT25256
0
0
1
1
0
1
0
1
None
1(1/4)
2(1/2)
3(All)
3000 - 3FFF 6000 - 7FFF
2000 - 3FFF 4000 - 7FFF
0000 - 3FFF 0000 - 7FFF
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
The WRSR instruction also allows the user to enable or
disable the write protect (WP) pin through the use of the
Write Protect Enable (WPEN) bit. Hardware write protec-
tion is enabled when the WP pin is low and the WPEN bit is
“1”. Hardware write protection is disabled when either the
WP pin is high or the WPEN bit is “0.” When the device is
hardware write protected, writes to the Status Register,
including the Block Protect bits and the WPEN bit, and the
block-protected sections in the memory array are disabled.
7
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