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AT24C128B-W-11

更新时间： 2024-11-24 03:23:19
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
23页 1008K
描述
Two-wire Serial EEPROM

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中文翻译

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AT24C128B-W-11 数据手册

 浏览型号AT24C128B-W-11的Datasheet PDF文件第2页浏览型号AT24C128B-W-11的Datasheet PDF文件第3页浏览型号AT24C128B-W-11的Datasheet PDF文件第4页浏览型号AT24C128B-W-11的Datasheet PDF文件第5页浏览型号AT24C128B-W-11的Datasheet PDF文件第6页浏览型号AT24C128B-W-11的Datasheet PDF文件第7页 
1. Features  
• Low-voltage and Standard-voltage Operation  
– 1.8 (VCC = 1.8V to 5.5V)  
• Internally Organized as 16,384 x 8  
• Two-wire Serial Interface  
• Schmitt Trigger, Filtered Inputs for Noise Suppression  
• Bidirectional Data Transfer Protocol  
• 1 MHz (5.5V, 2.5V), and 400 kHz (1.8V) Compatibility  
• Write Protect Pin for Hardware and Software Data Protection  
• 64-byte Page Write Mode (Partial Page Writes Allowed)  
• Self-timed Write Cycle (5 ms Max)  
Two-wire Serial  
EEPROM  
• High Reliability  
– Endurance: One Million Write Cycles  
128K (16,384 x 8)  
– Data Retention: 40 Years  
• Lead-free/Halogen-free  
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini MAP, 8-lead Ultra Lead  
Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 Packages  
• Die Sales: Wafer Form, Tape and Reel and Bumped Wafers  
AT24C128B  
2. Description  
The AT24C128B provides 131,072 bits of serial electrically erasable and programma-  
ble read-only memory (EEPROM) organized as 16,384 words of 8 bits each. The  
device’s cascadable feature allows up to eight devices to share a common two-wire  
bus. The device is optimized for use in many industrial and commercial applications  
where low-power and low-voltage operation are essential. The devices are available  
in space-saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini  
MAP, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball  
dBGA2 packages. In addition, the entire family is available in a 1.8V (5.5V to 3.6V)  
version.  
8-lead PDIP  
8-lead SOIC  
1
2
3
4
A0  
A1  
8
7
6
5
VCC  
WP  
8
7
6
5
A0  
A1  
1
2
3
4
VCC  
WP  
Table 0-1.  
Pin Configurations  
A2  
SCL  
SDA  
A2  
SCL  
SDA  
GND  
GND  
Pin Name  
A0–A2  
SDA  
Function  
Address Inputs  
Serial Data  
Serial Clock Input  
Write Protect  
Ground  
8-lead dBGA2  
8-lead TSSOP  
VCC  
8
7
6
5
1
2
3
4
A0  
8
7
6
5
A0  
1
2
3
4
VCC  
WP  
SCL  
SDA  
A1  
A1  
A2  
WP  
SCL  
A2  
SCL  
SDA  
GND  
GND  
WP  
Bottom View  
8-lead Ultra Lead Frame Land Grid Array  
GND  
8-lead Ultra Thin Mini MAP  
VCC  
WP  
8
7
6
5
1
2
3
4
A0  
VCC  
WP  
8
7
6
5
1
2
3
4
A0  
A1  
A1  
SCL  
SDA  
A2  
SCL  
SDA  
A2  
GND  
GND  
Bottom View  
Bottom View  
Rev. 5296A–SEEPR–1/08  
1234567...23

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