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AT22V10-25DM PDF预览

AT22V10-25DM

更新时间： 2024-01-22 03:45:33
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式输入元件可编程逻辑
页数 文件大小 规格书
11页 188K
描述
UV PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24

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中文翻译

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AT22V10-25DM 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：0.300 INCH, WINDOWED, CERDIP-24
针数：24Reach Compliance Code：unknown
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.27其他特性：10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
架构：PAL-TYPE最大时钟频率：30.3 MHz
JESD-30 代码：R-GDIP-T24JESD-609代码：e0
长度：32 mm专用输入次数：11
I/O 线路数量：10输入次数：22
输出次数：10产品条款数：132
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C组织：11 DEDICATED INPUTS, 10 I/O
输出函数：MACROCELL封装主体材料：CERAMIC, GLASS-SEALED
封装代码：WDIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE, WINDOW
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
可编程逻辑类型：UV PLD传播延迟：25 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Programmable Logic Devices最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mm

AT22V10-25DM 数据手册

 浏览型号AT22V10-25DM的Datasheet PDF文件第3页浏览型号AT22V10-25DM的Datasheet PDF文件第4页浏览型号AT22V10-25DM的Datasheet PDF文件第5页浏览型号AT22V10-25DM的Datasheet PDF文件第7页浏览型号AT22V10-25DM的Datasheet PDF文件第8页浏览型号AT22V10-25DM的Datasheet PDF文件第9页 
Preload of Registered Outputs  
The registers in the AT22V10 and AT22V10L are provided  
with circuitry to allow loading of each register asynchro-  
nously with either a high or a low. This feature will simplify  
testing since any state can be forced into the registers to con-  
trol test sequencing. A VIH level on the I/O pin will force the  
register high; a VIL will force it low, independent of the polarity  
bit (C0) setting. The preload state is entered by placing an  
11.5-V to  
Level forced on  
registered output pin  
during preload cycle  
Register state  
after cycle  
V
IH  
High  
Low  
V
IL  
13-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the  
clock pin is pulsed high, the data on the I/O pins is placed into  
the ten registers.  
tD  
tD  
tD  
tD  
tD  
tDMIN = 100 ns  
VH  
PRELOAD  
CLOCK  
REGISTERED  
OUTPUTS  
OUTPUT  
PRELOADENA. FORCEI/O’S PRELOADDATA  
OUTPUTSDIS. TO VIH ORVIL CLOCKEDIN  
VOLTAGE  
REMOVED  
PRELOAD  
DISABLED  
Power Up Reset  
3.8 V  
The registers in the AT22V10 and AT22V10L are designed to  
reset during power up. At a point delayed slightly from VCC  
crossing 3.8 V, all registers will be reset to the low state. The  
output state will depend on the polarity of the output buffer.  
POWER  
tPR  
This feature is critical for state machine initialization. How-  
ever, due to the asynchronous nature of reset and the uncer-  
tainty of how VCC actually rises in the system, the following  
conditions are required:  
REGISTERED  
OUTPUTS  
tS  
tW  
1) The VCC rise must be monotonic,  
CLOCK  
2) After reset occurs, all input and feedback setup times  
must be met before driving the clock pin high, and  
3) The clock must remain stable during tPR  
.
Description  
Parameter  
Min Typ Max Units  
Power-Up  
Reset Time  
t
600 1000  
ns  
PR  
Pin Capacitance (f = 1 MHz, T = 25°C) (1)  
Typ  
Max  
8
Units  
pF  
Conditions  
C
C
5
6
V
V
= 0 V  
IN  
IN  
8
pF  
= 0 V  
OUT  
OUT  
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.  
Erasure Characteristics  
The entire fuse array of an AT22V10 or AT22V10L is erased  
after exposure to ultraviolet light at a wavelength of 2537 Å.  
Complete erasure is assured after a minimum of 20 minutes  
exposure using 12,000 µW/cm2 intensity lamps spaced one  
inch away from the chip. Minimum erase time for lamps at  
other intensity ratings can be calculated from the minimum  
integrated erasure dose of 15 W•sec/cm2. To prevent unin-  
tentional erasure, an opaque label is recommended to cover  
the clear window on any UV erasable PLD which will be sub-  
jected to continuous fluorescent indoor lighting or sunlight.  
1-102  
AT22V10/L  
1...3456789...11

中文翻译

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AT22V10-25FM/883 ETC

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AT22V10-25GC ATMEL

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 		OT PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24
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 		OT PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24
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 		OT PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24
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 		OT PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24
AT22V10-25JC ATMEL

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 		OT PLD, 25ns, PAL-Type, CMOS, PQCC28, PLASTIC, MO-047AB, JLCC-28

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