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AT22V10-25GM PDF预览

AT22V10-25GM

更新时间: 2024-12-01 20:03:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟输入元件可编程逻辑
页数 文件大小 规格书
13页 531K
描述
OT PLD, 25ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, CERDIP-24

AT22V10-25GM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP24,.3
针数:24Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.24其他特性:10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
架构:PAL-TYPE最大时钟频率:30.3 MHz
JESD-30 代码:R-GDIP-T24JESD-609代码:e0
长度:32 mm专用输入次数:11
I/O 线路数量:10输入次数:22
输出次数:10产品条款数:132
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
可编程逻辑类型:OT PLD传播延迟:25 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

AT22V10-25GM 数据手册

 浏览型号AT22V10-25GM的Datasheet PDF文件第2页浏览型号AT22V10-25GM的Datasheet PDF文件第3页浏览型号AT22V10-25GM的Datasheet PDF文件第4页浏览型号AT22V10-25GM的Datasheet PDF文件第5页浏览型号AT22V10-25GM的Datasheet PDF文件第6页浏览型号AT22V10-25GM的Datasheet PDF文件第7页 
AT22V10/L  
Features  
High Speed Programmable Logic Device  
15 ns Max Propagation Delay  
5 V ±10% Operation  
Low Power CMOS Operation  
Speed  
Temp  
"L"  
Com./Mil. Com./Mil. Others  
12/15 90/100 55  
-15,-20  
All  
I (mA)  
CC  
CMOS and TTL Compatible Inputs and Outputs  
10 µA Leakage Maximum  
High Speed  
Reprogrammable - Tested 100% for Programmability  
High Reliability CMOS Technology  
2000 V ESD Protection  
200 mA Latchup Immunity  
Full Military, Commercial and Industrial Temperature Ranges  
Dual-In-Line and Surface Mount Packages  
UV Erasable  
Programmable  
Logic Device  
Logic Diagram  
Description  
The AT22V10 and AT22V10L are CMOS high performance EPROM-based Program-  
mable Logic Devices (PLDs). Speeds down to 15 ns and power dissipation as low as  
12 mA are offered. All speed ranges are specified over the full 5 V ±10% range. All  
pins offer a low ±10 µA leakage.  
The AT22V10L provides the optimum low power CMOS PLD solution, with low DC  
power (8 mA typical) and full CMOS output levels. The AT22V10L significantly re-  
duces total system power and enhances system reliability.  
Full CMOS output levels help reduce power in many other system components.  
The AT22V10 and AT22V10L incorporate a variable product term architecture. Each  
output is allocated from eight to 16 product terms, which allows highly complex logic  
functions to be realized.  
DIP/SOIC  
PLCC  
Pin Configurations  
Pin Name  
Function  
CLK/IN  
IN  
Clock and Logic Input  
Logic Inputs  
I/O  
Bidirectional Buffers  
No Internal Connection  
+5 V Supply  
*
VCC  
0023C  
1-97  

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