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AT17LV002-10JU-T PDF预览

AT17LV002-10JU-T

更新时间: 2024-11-18 14:40:55
品牌 Logo 应用领域
美国微芯 - MICROCHIP 时钟内存集成电路
页数 文件大小 规格书
23页 669K
描述
Configuration Memory, 2MX1, Serial, CMOS, PQCC20

AT17LV002-10JU-T 技术参数

是否Rohs认证:符合生命周期:Active
包装说明:LCC-20Reach Compliance Code:compliant
风险等级:5.76Is Samacsys:N
其他特性:IT CAN OPERATES ON 4.5-5.5 RANGE SUPPLY VOLTAGE ALSO最大时钟频率 (fCLK):10 MHz
JESD-30 代码:S-PQCC-J20JESD-609代码:e3
长度:8.966 mm内存密度:2097152 bit
内存集成电路类型:CONFIGURATION MEMORY内存宽度:1
功能数量:1端子数量:20
字数:2097152 words字数代码:2000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2MX1
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:SERIAL峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:4.572 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.966 mmBase Number Matches:1

AT17LV002-10JU-T 数据手册

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AT17LV65(1), AT17LV128(1), AT17LV256,  
AT17LV512, AT17LV010, AT17LV002, AT17LV040  
FPGA Configuration EEPROM Memory  
3.3V and 5.0V System Support  
Note 1.  
AT17LV65 and AT17LV128  
are Not Recommended for  
New Designs (NRND) and  
are Replaced by AT17LV256.  
DATASHEET  
Features  
EE Programmable Serial Memories Designed to Store Configuration Programs  
for Field Programmable Gate Arrays (FPGAs)  
̶
̶
̶
65,536 x 1-bit(1)  
131,072 x 1-bit(1)  
262,144 x 1-bit  
̶
̶
524,288 x 1-bit  
̶
̶
2,097,152 x 1-bit  
4,194,304 x 1-bit  
1,048,576 x 1-bit  
Supports both 3.3V and 5.0V Operating Voltage Applications  
In-System Programmable (ISP) via 2-wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera®  
FLEX®, APEXDevices, ORCA®, Xilinx® XC3000, XC4000, XC5200,  
Spartan®, Virtex® FPGAs  
Cascadable Read-back to Support Additional Configurations or Higher-density  
Arrays  
Very Low-power CMOS EEPROM Process  
Programmable Reset Polarity  
Available in 6mm x 6mm x 1mm 8-lead LAP (Pin-compatible with 8-lead SOIC  
Package), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and  
44-lead TQFP Packages  
Emulation of the Atmel AT24CXXX Serial EEPROMs  
Low-power Standby Mode  
High-reliability  
̶
̶
Endurance: 100,000 Write Cycles  
Data Retention: 90 Years for Industrial Parts (at 85C)  
Green (Pb/Halide-free/RoHS Compliant) Package Options Available  
Description  
The AT17LV FPGA Configuration EEPROMs (Configurators) provide an easy-to-  
use, cost-effective configuration memory solution for Field Programmable Gate  
Arrays. The AT17LV devices are packaged in the 8-lead LAP, 8-lead PDIP, 8-lead  
SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP options(Table 1). The  
AT17LV Configurators use a simple serial-access procedure to configure one or  
more FPGA devices. The user can select the polarity of the reset function during  
programming. These devices also support a write protection mechanism within its  
programming mode.  
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014  

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