Datasheet > AT1005S18

AT1005S18

更新时间： 2024-01-26 07:15:04

品牌	Logo	应用领域
POSEICO		/
页数	文件大小	规格书
4页	47K
描述
PHASE CONTROL THYRISTOR

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中文翻译

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数据手册

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AT1005S18 数据手册

Via N. Lorenzi 8 - I 16152 GENOVA - ITALY

Tel. int. +39/(0)10 6556549 - (0)10 6556488

Fax Int. +39/(0)10 6442510

Ansaldo Trasporti s.p.a.

Unita' Semiconduttori

ANSALDO

Tx 270318 ANSUSE I -

PHASE CONTROL THYRISTOR AT1005

Repetitive voltage up to

Mean on-state current

1800 V

1450 A

22.4 kA

Surge current

FINAL SPECIFICATION

feb 97 - ISSUE : 03

[°C]

Symbol

Characteristic

Conditions

Value

Unit

BLOCKING

V RRM

V RSM

V DRM

I RRM

I DRM

Repetitive peak reverse voltage

Non-repetitive peak reverse voltage

Repetitive peak off-state voltage

Repetitive peak reverse current

Repetitive peak off-state current

125 1800

125 1900

125 1800

V=VRRM

V=VDRM

125

CONDUCTING

I T (AV)

I TSM

I² t

Mean on-state current

Surge on-state current

I² t

180° sin, 50 Hz, Th=55°C, double side cooled

180° sin, 50 Hz, Tc=85°C, double side cooled

sine wave, 10 ms

1450

1190

125

22.4

without reverse voltage

2509 x1E3

1.75

A²s

V T

On-state voltage

On-state current = 2900 A

V T(TO)

r T

Threshold voltage

On-state slope resistance

125

0.92

125 0.260

mohm

SWITCHING

di/dt

dv/dt

Critical rate of rise of on-state current, min. From 75% VDRM up to 1580 A, gate 10V 5ohm 125

200

500

1.1

A/µs

V/µs

µs

Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM

125

Gate controlled delay time, typical

Circuit commutated turn-off time, typical

Reverse recovery charge

VD=100V, gate source 25V, 10 ohm , tr=.5 µs

dV/dt = 20 V/µs linear up to 75% VDRM

di/dt=-20 A/µs, I= 1050 A

VR= 50 V

250

µs

Q rr

I rr

I H

125

µC

Peak reverse recovery current

Holding current, typical

VD=5V, gate open circuit

VD=5V, tp=30µs

300

700

I L

Latching current, typical

GATE

V GT

Gate trigger voltage

VD=5V

3.5

300

0.25

I GT

Gate trigger current

VD=5V

V GD

V FGM

Non-trigger gate voltage, min.

Peak gate voltage (forward)

Peak gate current

VD=VDRM

125

FGM

V RGM

P GM

P G

Peak gate voltage (reverse)

Peak gate power dissipation

Average gate power dissipation

Pulse width 100 µs

150

MOUNTING

R th(j-h)

Thermal impedance, DC

Thermal impedance

Junction to heatsink, double side cooled

Case to heatsink, double side cooled

°C/kW

R th(c-h)

T j

Operating junction temperature

Mounting force

-30 / 125

18.0 / 20.0

500

°C

Mass

ORDERING INFORMATION : AT1005 S 18

VDRM&VRRM/100

standard specification

12 3 4

中文翻译

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与AT1005S18相关器件

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AT1006	MURATA	获取价格	Consumer Circuit, MODULE, SMT-6
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AT-1006(40)	HRS	获取价格	Fixed Attenuator, 0MHz Min, 8000MHz Max, ROHS COMPLIANT PACKAGE
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