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ASM5P23S08AF-1-16-ST PDF预览

ASM5P23S08AF-1-16-ST

更新时间： 2024-11-27 06:38:15
品牌 Logo 应用领域
PULSECORE 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
17页 385K
描述
3.3V ‘SpreadTrak’ Zero Delay Buffer

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ASM5P23S08AF-1-16-ST 技术参数

生命周期：Obsolete包装说明：0.150 INCH, ROHS COMPLIANT, SOIC-16
Reach Compliance Code：unknown风险等级：5.59
Is Samacsys：N系列：23S
输入调节：STANDARDJESD-30 代码：R-PDSO-G16
长度：9.905 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：16实输出次数：8
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1.75 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：3.9 mm
最小 fmax：133 MHzBase Number Matches：1

ASM5P23S08AF-1-16-ST 数据手册

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November 2006  
rev 1.5  
ASM5P23S08A  
3.3V ‘SpreadTrak’ Zero Delay Buffer  
General Features  
The ASM5P23S08A has two banks of four outputs each,  
which can be controlled by the select inputs as shown in  
the Select Input Decoding Table. The select input also  
allows the input clock to be directly applied to the outputs  
for chip and system testing purposes.  
•
Zero input - output propagation delay, adjustable by  
capacitive load on FBK input.  
•
Multiple configurations  
Configurations” Table.  
-
Refer “ASM5P23S08A  
•
•
Input frequency range: 15MHz to 133MHz  
Multiple low-skew outputs.  
• Output-output skew less than 200pS.  
• Device-device skew less than 700pS.  
• Two banks of four outputs, tri-stateable by two select  
inputs.  
Multiple ASM5P23S08A devices can accept the same input  
clock and distribute it. In this case the skew between the  
outputs of the two devices is guaranteed to be less than  
700pS.  
The ASM5P23S08A is available in five different  
configurations (Refer “ASM5P23S08A Configurations  
Table). The ASM5P23S08A-1 is the base part, where the  
output frequencies equal the reference if there is no  
counter in the feedback path. The ASM5P23S08A-1H is  
the high-drive version of the -1 and the rise and fall times  
on this device are faster.  
•
Less than 200pS cycle-to-cycle jitter  
(-1, -1H, -2, -3, -4, -5H).  
Available in 16 pin SOIC and TSSOP Packages.  
3.3V operation.  
Advanced 0.35µ CMOS technology.  
Industrial temperature available.  
‘SpreadTrak’.  
•
•
•
•
•
The ASM5P23S08A-2 allows the user to obtain 2X and 1X  
frequencies on each output bank. The exact configuration  
and output frequencies depends on which output drives the  
feedback pin. The ASM5P23S08A-3 allows the user to  
obtain 4X and 2X frequencies on the outputs.  
Functional Description  
ASM5P23S08A is a versatile, 3.3V zero-delay buffer  
designed to distribute high-speed clocks. It is available in a  
16 pin package. The part has an on-chip PLL, which locks  
to an input clock, presented on the REF pin. The PLL  
feedback is required to be driven to FBK pin, and can be  
obtained from one of the outputs. The input-to-output  
propagation delay is guaranteed to be less than 350pS,  
and the output-to-output skew is guaranteed to be less than  
250pS.  
The ASM5P23S08A-4 enables the user to obtain 2X clocks  
on all outputs. Thus, the part is extremely versatile, and  
can be used in a variety of applications.  
The ASM5P23S08A-5H is a high-drive version with REF/2  
on both banks  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  
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