Datasheet > ASM3P2872A

ASM3P2872A

更新时间： 2024-01-13 20:00:36

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	133K
描述
Peak EMI Reducing Solution

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中文翻译

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ASM3P2872A 数据手册

ASM3P2872A

Peak EMI

Reducing Solution

Features

• Generates an EMI optimized clock signal at the

The ASM3P2872A uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented by using a proprietary all digital method.

output.

• Integrated loop filter components.

• Operates with a 3.3V / 2.5V supply.

• Operating current less than 6mA.

• CMOS design.

The ASM3P2872A modulates the output of a single PLL

in order to “spread” the bandwidth of a synthesized clock,

and more importantly, decreases the peak amplitudes of

its harmonics. This results in significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation.’

• Input frequency range: 13MHz to 30MHz for 2.5V

13MHz to 30MHz for 3.3V

• Generates a 1X low EMI spread spectrum clock of

the input frequency.

• Frequency deviation: -1.25% @ 22MHz.

• Available in 6L-TSOP (6L-TSOT-23) packages.

Applications

The ASM3P2872A is targeted towards all portable

devices like MP3 players, Notebooks and digital still

cameras.

Product Description

The ASM3P2872A is

a versatile spread spectrum

frequency modulator designed specifically for a wide

range of clock frequencies. The ASM3P2872A reduces

electromagnetic interference (EMI) at the clock source,

allowing system wide reduction of EMI of all clock

dependent signals. The ASM3P2872A allows significant

system cost savings by reducing the number of circuit

board layers, ferrite beads and shielding that are

traditionally required to pass EMI regulations.

Key Specifications

Description

Supply voltages

Specification

VDD = 3.3V /2.5V

±200pS (Typ)

Cycle-to-Cycle Jitter

Output Duty Cycle

45/55% (worst case)

F_IN/640

Modulation Rate Equation

Frequency Deviation

-1.25% @ 22MHz

Block Diagram

VDD

PLL

Modulation

XIN

Crystal

Oscillator

Frequency

Divider

XOUT

Output

Divider

Phase

Detector

Loop

Filter

VCO

Feedback

Divider

ModOUT

REFOUT

VSS

JANUARY 2010 – Rev. 2

Publication Order Number:

ASM3P2872/D

12 3 4 5 6 7 8

中文翻译

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