ASM3P2863AF-08ST

更新时间： 2024-01-03 17:52:38

品牌	Logo	应用领域
PULSECORE		/
页数	文件大小	规格书
11页	391K
描述
Low Power Peak EMI Reducing Solution

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ASM3P2863AF-08ST 数据手册

January 2007

rev 0.3

ASM3P2863A

Low Power Peak EMI Reducing Solution

Features

The ASM3P2863A uses the most efficient and optimized

modulation profile approved by the FCC and is

implemented by using a proprietary all digital method.

•

Generates an EMI optimized clock signal at the

output.

•

Integrated loop filter components.

Operates with a 3.3V /2.5V supply.

Operating current less than 4mA.

Low power CMOS design.

Input frequency : 12MHz

Generates a 1X low EMI spread spectrum clock

of the input frequency.

Frequency deviation: ± 0.4%(Typ) @ 12MHz

Input Frequency

Available in 6-pin TSOT-23, 8-pin SOIC and 8-

pin TSSOP packages.

The ASM3P2863A modulates the output of a single PLL

in order to “spread” the bandwidth of a synthesized clock,

and more importantly, decreases the peak amplitudes of

its harmonics. This results in significantly lower system

EMI compared to the typical narrow band signal produced

by oscillators and most frequency generators. Lowering

EMI by increasing a signal’s bandwidth is called ‘spread

spectrum clock generation’.

•

Applications

The ASM3P2863A is targeted towards all portable

devices with very low power requirements like MP3

players, Notebooks and Digital still cameras.

Product Description

The ASM3P2863A is

a versatile spread spectrum

frequency modulator designed specifically for a wide

range of clock frequencies. The ASM3P2863A reduces

electromagnetic interference (EMI) at the clock source,

allowing system wide reduction of EMI of all clock

dependent signals. The ASM3P2863A allows significant

system cost savings by reducing the number of circuit

board layers ferrite beads, shielding that are traditionally

required to pass EMI regulations.

Key Specifications

Description

Supply voltages

Cycle-to-Cycle Jitter

Output Duty Cycle

Modulation Rate Equation

Frequency Deviation

Specification

V_DD= 2.5V / 3.3V

200 pS ( Max)

45/55% (worst case)

F_IN/256

± 0.4 % (Typ) @ 12MHz

Block Diagram

VDD

PLL

Modulation

XIN

Crystal

Frequency

Divider

Oscillator

XOUT

Output

Divider

Phase

Loop

Filter

VCO

Detector

Feedback

Divider

ModOUT

REFOUT

VSS

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

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ASM3P2863AF-08TR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
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ASM3P2863AG-06OR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
ASM3P2863AG-08SR	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
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ASM3P2863AG-08TT	PULSECORE	获取价格	Low Power Peak EMI Reducing Solution
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