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ASM3I622S01JG-08-TT PDF预览

ASM3I622S01JG-08-TT

更新时间： 2024-11-24 06:38:07
品牌 Logo 应用领域
PULSECORE 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
12页 484K
描述
Low Frequency Timing-Safe™ Peak EMI reduction IC

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ASM3I622S01JG-08-TT 技术参数

生命周期：Obsolete包装说明：4.40 MM, GREEN, TSSOP-8
Reach Compliance Code：unknown风险等级：5.84
Is Samacsys：NJESD-30 代码：R-PDSO-G8
长度：4.4 mm端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：20 MHz封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH主时钟/晶体标称频率：20 MHz
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：3 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHERBase Number Matches：1

ASM3I622S01JG-08-TT 数据手册

 浏览型号ASM3I622S01JG-08-TT的Datasheet PDF文件第2页浏览型号ASM3I622S01JG-08-TT的Datasheet PDF文件第3页浏览型号ASM3I622S01JG-08-TT的Datasheet PDF文件第4页浏览型号ASM3I622S01JG-08-TT的Datasheet PDF文件第5页浏览型号ASM3I622S01JG-08-TT的Datasheet PDF文件第6页浏览型号ASM3I622S01JG-08-TT的Datasheet PDF文件第7页 
May 2007  
rev 0.4  
ASM3P622S01B/J  
Low Frequency Timing-Safe™ Peak EMI reduction IC  
General Features  
eight-pin version and accepts one reference input and  
drives out one low-skew clock.  
•
Low Frequency Clock distribution with Timing-  
Safe™ Peak EMI Reduction  
All parts have on-chip PLLs that lock to an input clock on  
the REF pin. The PLL feedback is on-chip and is obtained  
from the CLKOUT pad, internal to the device.  
•
•
•
Input frequency range: 4MHz - 20MHz.  
Zero input - output propagation delay  
Low-skew outputs  
•
Output-output skew less than 250pS  
Device-device skew less than 700pS  
Multiple ASM3P622S01B/J devices can accept the same  
input clock and distribute it. In this case, the skew between  
the outputs of the two devices is guaranteed to be less than  
700pS.  
•
•
•
Less than 200pS cycle-to-cycle jitter  
Available in 8pin, 150 mil SOIC, 4.4mm TSSOP  
Package  
•
•
3.3V Operation  
Industrial temperature range  
Advanced CMOS technology  
The First True Drop-in Solution  
The output has less than 200pS of cycle-to-cycle jitter. The  
input and output propagation delay is guaranteed to be less  
than 250pS, and the output-to-output skew is guaranteed to  
be less than 250pS.  
•
•
Functional Description  
Refer “Spread Spectrum Control and Input-Output Skew  
Table”  
for deviations and Input-Output Skew for  
ASM3P622S01B/J is a versatile, 3.3V Zero-delay buffer  
designed to distribute low frequency Timing-Safe™ clocks  
with Peak EMI Reduction. The ASM3P622S01B/J is the  
ASM3P622S01B/J devices.  
Block Diagram  
VDD  
SSON  
SS%  
PLL  
Modulation  
XIN/CLKIN  
XOUT  
Reference  
Divider  
Crystal  
Oscillator  
Feedforward  
Divider  
Phase  
Loop  
Filter  
VCO  
Detector  
Feedback  
Divider  
CLKOUT  
GND  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  
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