September 2004
Preliminary Information
AS9C25512M2018L
AS9C25256M2018L
®
2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
•
Dual Chip enables on both ports for easy
depth expansion
•
True Dual-Port memory cells that allow simulta-
neous access of the same memory location
•
•
•
Interrupt and Collision Detection Features
2.5 V power supply for the core
LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
Snooze modes for each port for standby
operation
15mA typical standby current in power
down mode
Available in 256-pin Ball Grid Array
(BGA), 144-pin Thin Quad Flatpack
(TQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
[1]
•
•
Organisation: 524,288/262,144 × 18
Fully Synchronous, independent operation on
both ports
•
•
•
Selectable Pipeline or Flow-Through output
mode
Fast clock speeds in Pipeline output mode: 250
MHz operation (9Gbps bandwidth)
Fast clock to data access: 2.8ns for Pipeline out-
put mode
•
•
•
•
•
•
Asynchronous output enable control
Fast OE access times: 2.8ns
Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
•
Supports JTAG features compliant with
IEEE 1149.1
[1]
•
19/18 -bit counter with Increment, Hold and
Repeat features on each port
Note:
1. AS9C25512M2018L/AS9C25256M2018L
Selection guide
Feature
-250
4
-200
5
-166
6
-133
7.5
133
4.2
83
Units
ns
Minimum cycle time
Maximum Pipeline clock frequency
Maximum Pipeline clock access time
Maximum flow-through clock frequency
Maximum flow-through clock access time
Maximum operating current
250
2.8
150
6.5
TBD
18
200
3.4
133
7.5
350
18
166
3.6
100
10
MHz
ns
MHz
ns
12
300
18
260
18
mA
mA
Maximum snooze mode current
9/24/04; v.1.2
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