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AS91L1001BU10F100I PDF预览

AS91L1001BU10F100I

更新时间: 2022-11-24 21:46:36
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其他 - ETC /
页数 文件大小 规格书
28页 568K
描述
The AS91L1006BU is a one to 6-port JTAG gateway

AS91L1001BU10F100I 数据手册

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July 2004  
AS91L1006BU  
If the LSP is not parked in a stable state,  
MODE_SELECT Register  
The Mode_Select register allows the LSP  
of the AS91L1006BU to be connected in various  
different configurations. A LSP is selected for  
connection within the scan chain by the contents of  
the Mode_Select register.  
i.e.: Pause-DR, Pause-IR, Run-Test-Idle or Test-  
Logic-Reset, it will be connected into the active  
scan chain. If all LSPs are parked in a stable  
state, then the AS91L1006BU will perform a  
bypass of the 6-LSP chain section. In this way if  
both sections are in the bypass mode then the  
AS91L1006BU is performing a loopback of TDI-  
>Register->TDO to the host device.  
Mode_Select  
LSP Configuration (If Port  
Register (Bit 15  
Unparked)  
Mode_Select  
LSP Configuration (If Port  
Register (Bit 7 ->  
Unparked)  
-> Bit 8)  
Bit 0)  
XXX0X000  
XXX0X001  
XXX0X010  
XXX0X011  
TDI ->Register->LSP_Data  
XXX0X000  
XXX0X001  
XXX0X010  
XXX0X011  
LSP_Data ->TDO  
TDI ->Register->LSP1->PAD->  
LSP_Data  
LSP_Data ->LSP4->PAD-  
>TDO  
TDI ->Register->LSP2->PAD->  
LSP_Data  
LSP_Data ->LSP5->PAD-  
>TDO  
TDI ->Register->LSP1->PAD-  
>LSP2->PAD-> LSP_Data  
LSP_Data ->LSP4->PAD-  
>LSP5->PAD->TDO  
XXX0X100  
XXX0X101  
TDI ->Register->LSP3->PAD->  
LSP_Data  
XXX0X100  
XXX0X101  
LSP_Data ->LSP6->PAD-  
>TDO  
TDI ->Register->LSP1->PAD-  
>LSP3->PAD-> LSP_Data  
LSP_Data ->LSP4->PAD-  
>LSP6->PAD->TDO  
XXX0X110  
XXX0X111  
TDI ->Register->LSP2->PAD-  
>LSP3->PAD-> LSP_Data  
XXX0X110  
XXX0X111  
LSP_Data ->LSP5->PAD-  
>LSP6->PAD->TDO  
TDI ->Register->LSP1->PAD-  
>LSP2->PAD->LSP3->PAD->  
LSP_Data  
LSP_Data ->LSP4->PAD-  
>LSP5->PAD->LSP6->PAD-  
>TDO  
Table 7 - Mode Select Register Mapping  
X = Don’t care  
Register = AS91L1006BU device instruction register or any of the AS91L1006BU device test  
data registers.  
PAD = Insertion of a 1-bit register for data synchronization.  
Upon entering Test-Logic-Reset, the register bits will be loaded with “0000000”.  
www.alsc.com  
Alliance Semiconductor  
2003, 2004 © Copyright Alliance Semiconductor Corporation. All Rights reserved.  
8

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