Datasheet > 存储 > SRAM> AS7C4096A-12TCN

AS7C4096A-12TCN

更新时间： 2024-02-02 15:27:09

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器光电二极管 ISM频段 PC
页数	文件大小	规格书
10页	325K
描述
5.0V 512K x 8 CMOS SRAM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AS7C4096A-12TCN 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSOP2
包装说明：	TSOP2,	针数：	44
Reach Compliance Code：	compliant	Factory Lead Time：	8 weeks
风险等级：	5.68	最长访问时间：	12 ns
JESD-30 代码：	R-PDSO-G44	长度：	18.415 mm
内存密度：	4194304 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	8	功能数量：	1
端子数量：	44	字数：	524288 words
字数代码：	512000	工作模式：	ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	512KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	1.2 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	10.16 mm	Base Number Matches：	1

AS7C4096A-12TCN 数据手册

AS7C4096A

Functional description

The AS7C4096A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as

524,288 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are

desired.

Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5/6 ns are ideal

AA RC WC

for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory

systems.

When CE is high the device enters standby mode. The device is guaranteed not to exceed 55mW power consumption in CMOS

standby mode.

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written

on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins

only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip

drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write

enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5.0V supply voltage. This device is available as

per industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.

Absolute maximum ratings

Parameter

Symbol

Min

–0.5

–

Max

Unit

Voltage on V relative to GND

+7.0

Voltage on any pin relative to GND

Power dissipation

+0.5

1.0

Storage temperature (plastic)

–65

–55

–

+150

+125

°C

stg

Temperature with V applied

bias

DC current into output (low)

OUT

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-

tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Data

Mode

Standby (I , I

)

High Z

SB SB1

Output disable (I

)

High Z

Read (I

)

OUT

Write (I

)

5/27/05, v. 1.1

Alliance Semiconductor

P. 2 of 10

123 4 5 6 7...10

下载PDF

与AS7C4096A-12TCN相关器件

型号	品牌	描述	获取价格	数据表
AS7C4096A-12TI	ALSC	5.0V 512K x 8 CMOS SRAM	获取价格
AS7C4096A-12TIN	ALSC	5.0V 512K x 8 CMOS SRAM	获取价格
AS7C4096A-15JC	ALSC	5.0V 512K x 8 CMOS SRAM	获取价格
AS7C4096A-15JCN	ALSC	5.0V 512K x 8 CMOS SRAM	获取价格
AS7C4096A-15JI	ALSC	5.0V 512K x 8 CMOS SRAM	获取价格
AS7C4096A-15JIN	ALSC	5.0V 512K x 8 CMOS SRAM	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

AS7C4096A-12TCN

AS7C4096A-12TCN 技术参数

AS7C4096A-12TCN 数据手册

与AS7C4096A-12TCN相关器件

与AS7C4096A-12TCN相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AS7C4096A-12TCN

AS7C4096A-12TCN 技术参数

AS7C4096A-12TCN 数据手册

与AS7C4096A-12TCN相关器件

与AS7C4096A-12TCN相关文章

您还可以找

您在本页遇到什么问题？