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AS7C34096-20JC PDF预览

AS7C34096-20JC

更新时间： 2024-01-31 23:58:14
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
9页 247K
描述
5V/3.3V 512K X8 CMOS SRAM

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AS7C34096-20JC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：44
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.66
Is Samacsys：N最长访问时间：20 ns
JESD-30 代码：R-PDSO-G44JESD-609代码：e3/e6
长度：18.415 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：44
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX8
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN/TIN BISMUTH端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：10.16 mm
Base Number Matches：1

AS7C34096-20JC 数据手册

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AS7C4096  
AS7C34096  
®
Functional description  
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices  
organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple  
interfacing are desired.  
Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5/6/7/8 ns are  
AA RC WC  
OE  
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank  
memory systems.  
When CE is high the device enters standby mode. The AS7C4096/AS7C34096 is guaranteed not to exceed 110/72 mW power  
consumption in CMOS standby mode.  
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is  
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/  
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).  
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip  
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or  
write enable is active, output drivers stay in high-impedance mode.  
All chip inputs and outputs are TTL-compatible, and operation is from either a single 5V(AS7C4096) or 3.3V(AS7C34096)  
supply. Both devices are available in the JEDEC standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.  
Absolute maximum ratings  
Parameter  
Device  
Symbol  
Min  
–1  
Max  
+7.0  
+5.0  
Unit  
V
AS7C4096  
AS7C34096  
V
V
V
t1  
t1  
t2  
D
Voltage on V relative to GND  
CC  
–0.5  
–0.5  
–
V
Voltage on any pin relative to GND  
Power dissipation  
V
+0.5  
V
CC  
P
T
1.0  
W
Storage temperature  
–65  
–55  
–
+150  
+125  
20  
°C  
°C  
mA  
stg  
bias  
Temperature with V applied  
T
CC  
DC current unto output (low)  
I
OUT  
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-  
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect reliability.  
Truth table  
CE  
H
L
WE  
X
OE  
X
Data  
Mode  
Standby (I , I  
High Z  
High Z  
)
SB SB1  
H
H
Output disable (I  
)
CC  
L
H
L
D
Read (I  
)
CC  
OUT  
L
L
X
D
Write (I  
)
IN  
CC  
Key: X = Don’t care, L = Low, H = High  
1/13/05; v.1.9  
Alliance Semiconductor  
P. 2 of 9  
1234567...9

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