Datasheet > AS7C34096-10TCH

AS7C34096-10TCH

更新时间： 2022-12-01 20:41:33

品牌	Logo	应用领域
ALSC		静态存储器光电二极管
页数	文件大小	规格书
10页	269K
描述
Standard SRAM, 512KX8, 10ns, CMOS, PDSO44, TSOP2-44

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AS7C34096-10TCH 数据手册

AS7C4096

AS7C34096

Functional description

The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices

organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple

interfacing are desired.

Equal address access and cycle times (t_AA, t_RC, t_WC) of 10/12/15/20 ns with output enable access times (t_OE) of 5/6/7/8 ns are

ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory

systems.

When CE is high the device enters standby mode. The AS7C4096 is guaranteed not to exceed 110 mW power consumption in

CMOS standby mode.

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is written

on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins

only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives

I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write

enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single supply voltage. Both devices are available in the

industry standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.

Absolute maximum ratings

Parameter

Device

Symbol

V_t1

Min

–1

Max

+7.0

+5.0

V_CC+0.5

1.0

Unit

AS7C4096

AS7C34096

Voltage on V_CCrelative to GND

V_t1

–0.5

–

Voltage on any pin relative to GND

Power dissipation

V_t2

P_D

°C

Storage temperature (plastic)

Temperature with V_CCapplied

DC current unto output (low)

T_stg

–65

–55

–

+150

+125

T_bias

I_OUT

NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-

ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

Truth table

Data

High Z

D_OUT

D_IN

Mode

Standby (I_SB, I_SB1

)

Output disable (I_CC)

Read (I_CC)

Write (I_CC)

Key: X = Don’t care, L = Low, H = High

11/28/01; v.1.7

Alliance Semiconductor

P. 2 of 10

123 4 5 6 7...10

下载PDF

与AS7C34096-10TCH相关器件

型号	品牌	描述	获取价格	数据表
AS7C34096-10TCN	ALSC	5V/3.3V 512K X8 CMOS SRAM	获取价格
AS7C34096-12	ALSC	5V/3.3V 512K X8 CMOS SRAM	获取价格
AS7C34096-12JC	ALSC	5V/3.3V 512K X8 CMOS SRAM	获取价格
AS7C34096-12JCN	ALSC	5V/3.3V 512K X8 CMOS SRAM	获取价格
AS7C34096-12JI	ALSC	5V/3.3V 512K X8 CMOS SRAM	获取价格
AS7C34096-12JIN	ALSC	5V/3.3V 512K X8 CMOS SRAM	获取价格