Datasheet > AS7C34096-10BCH

AS7C34096-10BCH

更新时间： 2022-12-01 20:41:33

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
10页	269K
描述
Standard SRAM, 512KX8, 10ns, CMOS, PBGA48, 7 X 11 MM, CSP, FBGA-48

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AS7C34096-10BCH 数据手册

AS7C4096

AS7C34096

AC test conditions

- Output load: see Figure B or Figure C.

- Input pulse level: GND to 3.0V. See Figures A, B, and C.

- Input rise and fall times: 2 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

Thevenin equivalent:

168W

+1.728V

OUT

+5V

+3.3V

320W

480W

+3.0V

GND

OUT

90%

10%

90%

10%

255W

C(14)

GND

350W

C(14)

GND

2 ns

Figure A: Input pulse

Figure C: 3.3V Output load

Figure B: 5V Output load

Notes

During V power-up, a pull-up resistor to V on CE is required to meet I specification.

CC CC SB

This parameter is sampled, but not 100% tested.

For test conditions, see AC Test Conditions.

and t

are specified with C = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage.

CHZ L

CLZ

This parameter is guaranteed, but not tested.

WE is HIGH for read cycle.

CE and OE are LOW for read cycle.

Address valid prior to or coincident with CE transition Low.

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 Not applicable.

13 C = 30pF, except at high Z and low Z parameters, where C = 5pF.

11/28/01; v.1.7

Alliance Semiconductor

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1...3 4 567 8 9 10

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