December 2001
AS7C4096
AS7C34096
®
5V/3.3V 512K × 8 CMOS SRAM
Features
• AS7C4096 (5V version)
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 468 mW (AS7C34096) / max @ 12 ns
Pin arrangements
Logic block diagram
36-pin SOJ (400 mil)
44-pin TSOP 2
NC
NC
NC
NC
NC
A18
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
2
V
CC
2
A18
A17
A16
A15
OE
A0
A1
3
A2
3
4
GND
A3
4
A2
A17
A16
A15
OE
5
A4
5
A3
6
Input buffer
CE
6
A4
7
I/O1
I/O2
VCC
GND
I/O3
I/O4
WE
A5
7
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
CE
8
8
I/O1
I/O2
VCC
I/O8
I/O7
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
11
12
13
14
15
16
17
18
GND
I/O1
I/O8
VCC
GND
I/O3
I/O4
WE
A5
524,288 × 8
Array
(4,194,304)
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A6
A7
A6
A8
A7
A9
A8
A9
A9
NC
NC
NC
NC
Column decoder
WE
OE
CE
Control
Circuit
48-CSP/BGA Package
1
2
3
4
5
6
A
B
A0
A1
NC
WE
NC
NC
NC
A18
CS
A3
A6
A8
I/O5
I/O6
VSS
A2
A4
A7
I/O1
I/O2
VCC
C
D
E
NC
NC
NC
NC
OE
A10
A5
NC
NC
NC
NC
NC
NC
A17
A16
A12
VCC
I/O7
I/O8
A9
VSS
F
I/O3
I/O4
A14
G
H
A15
A13
A11
Selection guide
–10
10
5
–12
–15
–20
20
Unit
Maximum address access time
12
6
15
7
ns
Maximum outputenable access time
9
ns
AS7C4096
AS7C34096
AS7C4096
AS7C34096
–
250
130
20
220
110
20
180
100
20
mA
mA
mA
mA
Maximum operating current
160
–
Maximum CMOS standby current
20
20
20
20
11/28/01; v.1.7
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