Datasheet > AS7C33512PFS32A-225TQI

AS7C33512PFS32A-225TQI

更新时间： 2024-01-10 06:44:13

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
21页	463K
描述
Standard SRAM, 512KX32, 6.9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

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AS7C33512PFS32A

AS7C33512PFS36A

Signal descriptions

CLK

A0–A19

I/ O Properties Description

CLOCK Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock.

SYNC

Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.

Data. Driven as output when the chip is enabled and when OE is active.

DQ[a,b,c,d] I/ O

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is

inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.

CE0

SYNC

Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges

when ADSC is active or when CE0 and ADSP are active.

CE1, CE2

ADSP

ADSC

ADV

SYNC

Address strobe processor. Asserted low to load a new address or to enter standby mode.

Address strobe controller. Asserted low to load a new address or to enter standby mode.

Advance. Asserted low to continue burst read/ write.

Global write enable. Asserted low to write all 32/ 36 and 18 bits. When high, BWE and

BW[a:d] control write enable.

GWE

BWE

SYNC

Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.

Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If

any of BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d]

are inactive, the cycle is a read cycle.

BW[a,b,c,d]

SYNC

ASYNC Asynchronous output enable. I/ O pins are driven when OE is active and chip is in read mode.

Count mode. When driven high, count sequence follows Intel XOR convention. When driven

STATIC

LBO

low, count sequence follows linear convention. This signal is internally pulled high.

TDO

TDI

SYNC

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA

only).

TMS

TCK

SYNC

Test Clock

STATIC

Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the

falling edge of TCK.

Flow-through mode.When low, enables single register flow-through mode. Connect to V_DDif

unused or for pipelined operation.

ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

Write enable truth table (per byte)

Function

GWE BWE BWa

BWb

BWc BWd

Write All Bytes

Write Byte a

Write Byte c and d

Read

ꢀꢁꢂꢃꢄX = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.

12/ 2/ 02, v. 0.9.8 Advance Info

Alliance Semiconductor

4 of 21

1 2 345 6 7...21

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型号	品牌	描述	获取价格	数据表
AS7C33512PFS32A-250BC	ALSC	Standard SRAM, 512KX32, 6.5ns, CMOS, PBGA165, BGA-165	获取价格
AS7C33512PFS32A-250TQC	ALSC	Standard SRAM, 512KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格
AS7C33512PFS36A-133TQC	ALSC	3.3V 512K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33512PFS36A-133TQCN	ALSC	3.3V 512K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33512PFS36A-133TQI	ALSC	3.3V 512K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33512PFS36A-133TQIN	ALSC	3.3V 512K x 32/36 pipelined burst synchronous SRAM	获取价格

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