Datasheet > AS7C33256PFS32A2-166TQC

AS7C33256PFS32A2-166TQC

更新时间： 2022-12-01 22:43:53

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器
页数	文件大小	规格书
14页	384K
描述
Standard SRAM, 256KX32, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

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AS7C33256PFS32A

AS7C33256PFS36A

Signal descriptions

Signal

I/O Properties Description

CLK

CLOCK

SYNC

Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.

Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

Data. Driven as output when the chip is enabled and OE is active.

A0–A17

DQ[a,b,c,d] I/O

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is

inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.

CE0

SYNC

Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock

edges when ADSC is active or when CE0 and ADSP are active.

CE1, CE2

ADSP

Address strobe processor. Asserted LOW to load a new bus address or to enter standby

mode.

ADSC

ADV

SYNC

Address strobe controller. Asserted LOW to load a new address or to enter standby mode.

Advance. Asserted LOW to continue burst read/write.

Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]

control write enable.

GWE

BWE

SYNC

Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.

Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =

Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write

cycle. If all BW[a:d] are inactive the cycle is a read cycle.

BW[a,b,c,d]

SYNC

Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read

mode.

ASYNC

STATIC

Count mode. When driven High, count sequence follows Intel XOR convention. When

driven Low, count sequence follows linear convention. This signal is internally pulled High.

LBO

Flow-through mode.When low, enables single register flow-through mode. Connect to

STATIC

ASYNC

V_DDif unused or for pipelined operation.

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

Absolute maximum ratings

Parameter

Symbol

V_DD, V_DDQ

V_IN

Min

–0.5

–

Max

+4.6

Unit

Power supply voltage relative to GND

Input voltage relative to GND (input pins)

Input voltage relative to GND (I/O pins)

Power dissipation

V_DD+ 0.5

V_DDQ+ 0.5

1.8

V_IN

P_D

^oC

DC output current

I_OUT

–

Storage temperature (plastic)

Temperature under bias

T_stg

–65

+150

T_bias

+135

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum

rating conditions may affect reliability.

4/15/02; v.1.9

Alliance Semiconductor

P. 5 of 14

1 2 3 456 7 8...14

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与AS7C33256PFS32A2-166TQC相关器件

型号	品牌	描述	获取价格	数据表
AS7C33256PFS32A2-166TQI	ISSI	Standard SRAM, 256KX32, 9ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格
AS7C33256PFS36A	ALSC	3.3V 256K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33256PFS36A-100BC	ISSI	Standard SRAM, 256KX36, 12ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFS36A-100BI	ISSI	Standard SRAM, 256KX36, 12ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFS36A-133BC	ALSC	Standard SRAM, 256KX36, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFS36A-133BI	ISSI	Standard SRAM, 256KX36, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格

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