Datasheet > 存储 > SRAM> AS7C33256PFS32A-166TQI

AS7C33256PFS32A-166TQI

更新时间： 2024-02-08 11:16:56

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
20页	528K
描述
3.3V 256K x 32/36 pipelined burst synchronous SRAM

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AS7C33256PFS32A-166TQI 数据手册

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AS7C33256PFS32A

AS7C33256PFS36A

DC electrical characteristics for 3.3V I/O operation

Parameter

Input leakage current¹

Output leakage current

Sym

|I_LI|

Conditions

V_DD= Max, 0V < V_IN< V_DD

OE ≥ V_IH, V_DD= Max, 0V < V_OUT< V_DDQ

Address and control pins

I/O pins

Min

-2

Max

Unit

µA

|I_LO

-2

2^*

-0.3^**

-0.5^**

2.4

–

V_DD+0.3

V_DDQ+0.3

0.8

µA

Input high (logic 1) voltage

Input low (logic 0) voltage

V_IH

Address and control pins

I/O pins

V_IL

0.8

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –4 mA, V_DDQ= 3.135V

I_OL= 8 mA, V_DDQ= 3.465V

–

0.4

1 LBO, and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.

DC electrical characteristics for 2.5V I/O operation

Parameter

Input leakage current

Output leakage current

Sym

|I_LI|

Conditions

V_DD= Max, 0V < V_IN< V_DD

OE ≥ V_IH, V_DD= Max, 0V < V_OUT< V_DDQ

Address and control pins

I/O pins

Min

-2

Max

Unit

µA

|I_LO

-2

V_DD+0.3

V_DDQ+0.3

0.7

1.7^*

-0.3^**

1.7

Input high (logic 1) voltage

Input low (logic 0) voltage

V_IH

Address and control pins

I/O pins

V_IL

0.7

Output high voltage

Output low voltage

V_OH

V_OL

I_OH= –4 mA, V_DDQ= 2.375V

I_OL= 8 mA, V_DDQ= 2.625V

–

0.7

^*V_IHmax < VDD +1.5V for pulse width less than 0.2 X t_CYC

min = -1.5 for pulse width less than 0.2 X t_CYC

operating conditions and maximum limits

Parameter

Sym

Conditions

-166

-133

Unit

CE0 < V_IL, CE1 > V_IH, CE2 < V_IL, f = f_Max

Operating power supply current¹

I_CC

475

130

425

I_OUT= 0 mA, ZZ < V_IL

All V_IN≤ 0.2V or >

– 0.2V, Deselected,

I_SB

100

f = f_Max, ZZ < V_IL

Deselected, f = 0, ZZ < 0.2V,

all V_IN≤ 0.2V or ≥ V_DD– 0.2V

Standby power supply current

I_SB1

I_SB2

Deselected, f = f , ZZ

≥

– 0.2V,

Max

all V_IN≤ V_ILor ≥ V_IH

1 I given with no output loading. I increases with faster cycle times and greater output loading.

11/30/04, v.3.1

Alliance Semiconductor

P. 9 of 20

1...6 7 8910 11 12...20

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