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AS6UA5128-55HFC PDF预览

AS6UA5128-55HFC

更新时间: 2024-02-21 22:18:53
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
11页 218K
描述
SRAM

AS6UA5128-55HFC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.92

AS6UA5128-55HFC 数据手册

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AS6UA5128  
Functional description  
The AS6UA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288  
words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.  
Equal address access and cycle times (tAA, tRC, tWC) of 55/ 70/ 100 ns are ideal for low-power applications. Active high and  
low chip selects (CS) permit easy memory expansion with multiple-bank memory systems.  
When CS is high, the device enters standby mode: the AS6UA5128 is guaranteed not to exceed 72 µW power consumption at  
3.6V and 55 ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device also returns data when VCC is reduced to  
1.5V for even lower power consumption.  
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low. Data on the input pins I/ O1–I/ O8 is  
written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive  
I/ O pins only after outputs have been disabled with output enable ( OE) or write enable (WE).  
A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives  
I/ O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write  
enable is active, output drivers stay in high-impedance mode.  
All chip inputs and outputs are CMOS-compatible, and operation is from a single 1.65V to 3.6V supply. The device is available  
in the JEDEC standard 32-pin TSOP I, 32-pin sTSOP I, 400-mL TSOP II, and 36(48)-ball FBGA packages.  
Absolute maximum ratings  
Parameter  
Device  
Symbol  
Min  
–0.5  
–0.5  
Max  
Unit  
V
Voltage on VCC relative to V  
V
VCC + 0.5  
SS  
tIN  
Voltage on any I/ O pin relative to GND  
Power dissipation  
V
V
tI/ O  
PD  
1.0  
+150  
+125  
20  
W
Storage temperature (plastic)  
Temperature with VCC applied  
DC output current (low)  
Tstg  
Tbias  
IOUT  
–65  
–55  
°C  
°C  
mA  
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect reliability.  
Truth table  
CS  
H
L
WE  
X
OE  
X
Supply Current  
ISB  
I/ O1–I/ O8  
High Z  
Mode  
Standby (ISB)  
X
X
L
H
H
ICC  
ICC  
ICC  
High Z  
DOUT  
Output disable (ICC)  
Read (ICC)  
L
H
L
L
L
X
D
Write (ICC)  
IN  
Key: X = Dont care, L = Low, H = High.  
2
ALLIANCE SEMICONDUCTOR  
7/ 14/ 00