Datasheet > AS4LC1M16EC-7

AS4LC1M16EC-7

更新时间： 2024-02-07 09:04:54

品牌	Logo	应用领域
MICROSS		动态存储器
页数	文件大小	规格书
22页	195K
描述
DRAM

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数据手册

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AS4LC1M16EC-7 数据手册

AS4LC1M16 883C

1 MEG x 16 DRAM

AUSTIN SEMICONDUCTOR, INC.

PRELIMINARY

RAS-ONLY REFRESH CYCLE

RAS

RPC

CRP

CASL/CASH

RAH

ASR

ADDR

ROW

OPEN

WRH

WRP

WRH

WRP

NOTE 1

CBR REFRESH CYCLE

(Addresses and OE = DON’T CARE)

RAS

RPC

CHR

RPC

CSR

CHR

CSR

CASL and CASH

OPEN

WRH

WRP

WRH

WRP

NOTE 2

NOTE:

1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should

implement WE HIGH for ^tWRP and ^tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.

2. WRP and ^tWRH are for system design reference only. The WE signal is actually a “don’t care” at RAS time during a CBR

REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to ensure compatibility with other

DRAMs that require WE HIGH at RAS time during a CBR REFRESH.

TIMING PARAMETERS

-6

-7

-8

-6

-7

-8

SYM MIN

MAX

MIN

MAX

MIN

MAX

UNITS

SYM MIN

MAX

MIN

MAX

MIN

MAX

UNITS

^tASR

^tCHR

^tCP

^tCRP

^tCSR

^tRAH

^tRAS

^tRC

^tRP

^tRPC

^tWRH

^tWRP

60 10,000

70 10,000 80 10,000

105

125

150

AS4LC1M16

REV. 3/97

DS000020

Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

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