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AS4DDR232M64PBG-3/IT PDF预览

AS4DDR232M64PBG-3/IT

更新时间: 2024-01-10 17:38:25
品牌 Logo 应用领域
MICROSS 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
28页 300K
描述
DDR DRAM, 32MX64, 0.45ns, CMOS, PBGA255, 25 X 32 MM, 1.27 MM PITCH, PLASTIC, BGA-255

AS4DDR232M64PBG-3/IT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:BGA,针数:255
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.17
访问模式:FOUR BANK PAGE BURST最长访问时间:0.45 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B255
JESD-609代码:e0长度:32 mm
内存密度:2147483648 bit内存集成电路类型:DDR DRAM
内存宽度:64功能数量:1
端口数量:1端子数量:255
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32MX64
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
自我刷新:YES最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:25 mmBase Number Matches:1

AS4DDR232M64PBG-3/IT 数据手册

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iPEM  
2.1 Gb SDRAM-DDR2  
AS4DDR232M64PBG  
32Mx64 DDR2 SDRAM  
iNTEGRATED Plastic Encapsulated Microcircuit  
FEATURES  
BENEFITS  
DDR2 Data rate = 667, 533, 400  
SPACE conscious PBGA dened for easy  
Available in Industrial, Enhanced and Military Temp  
Package:  
SMT manufacturability (50 mil ball pitch)  
Reduced part count  
47% I/O reduction vs Individual CSP approach  
Reduced trace lengths for lower parasitic  
capacitance  
255 Plastic Ball Grid Array (PBGA), 25 x 32mm  
1.27mm pitch  
Differential data strobe (DQS, DQS#) per byte  
Internal, pipelined, double data rate architecture  
4-bit prefetch architecture  
DLL for alignment of DQ and DQS transitions with  
clock signal  
Suitable for hi-reliability applications  
Upgradable to 64M x 64 density  
(consult factory for info on  
AS4DDR264M64PBG)  
Four internal banks for concurrent operation  
(Per DDR2 SDRAM Die)  
ConfigurationAddressing  
Programmable Burst lengths: 4 or 8  
Auto Refresh and Self Refresh Modes  
On Die Termination (ODT)  
Adjustable data – output drive strength  
1.8V ±0.1V power supply and I/O (VCC/VCCQ)  
Programmable CAS latency: 3, 4, 5, or 6  
Posted CAS additive latency: 0, 1, 2, 3 or 4  
Write latency = Read latency - 1* tCK  
Organized as 32M x 64  
Parameter  
32Megx72  
Configuration  
RefreshCount  
RowAddress  
BankAddress  
ColumnAddress  
8Megx16x4Banks  
8K  
8K(A0ͲA12)  
4(BA0ͲBA1)  
1K(A0ͲA9)  
Weight: AS4DDR232M64PBG ~ 3.5 grams typical  
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only  
FUNCTIONAL BLOCK DIAGRAM  
Ax, BA0-2  
ODT  
VRef  
VCC  
VCCQ  
VSS  
VSSQ  
VCCL  
VCCL  
VCCL  
VCCL  
VSSDL  
VSSDL  
VSSDL  
VSSDL  
A
B
C
D
2
2
2
2
2
2
2
2
CS0\  
CS1\  
CS2\  
CS3\  
2
2
2
2
3
3
3
3
3
3
3
3
UDMx, LDMx  
UDSQx,UDSQx\  
LDSQx, LDSQx\  
RASx\,CASx\,WEx\  
CKx,CKx\,CKEx  
C
B
DQ16-31  
A
DQ0-15  
DQ32-47  
AS4DDR232M64PBG  
Rev. 1.4 01/10  
Micross Components reserves the right to change products or specications without notice.  
1

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