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AS4DDR232M64PBG-38/XT PDF预览

AS4DDR232M64PBG-38/XT

更新时间: 2024-02-08 07:39:18
品牌 Logo 应用领域
AUSTIN 内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
28页 363K
描述
32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

AS4DDR232M64PBG-38/XT 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:255
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.17
Is Samacsys:N访问模式:FOUR BANK PAGE BURST
最长访问时间:0.5 ns其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PBGA-B255JESD-609代码:e0
长度:32 mm内存密度:2147483648 bit
内存集成电路类型:DDR DRAM内存宽度:64
功能数量:1端口数量:1
端子数量:255字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32MX64封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:RECTANGULAR
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:2.03 mm
自我刷新:YES最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:25 mmBase Number Matches:1

AS4DDR232M64PBG-38/XT 数据手册

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iPEM  
2.1 Gb SDRAM-DDR2  
Austin Semiconductor, Inc.  
AS4DDR232M64PBG  
32Mx64 DDR2 SDRAM  
iNTEGRATED Plastic Encapsulated Microcircuit  
BENEFITS  
FEATURES  
„
„
„
DDR2 Data rate = 667, 533, 400  
„
SPAꢁE conscious PBGA defined for easy  
SMT manufacturability (50 mil ball pitch)  
Reduced part count  
Available in Industrial, Enhanced and Military Temp  
Package:  
„
„
„
255 Plastic Ball Grid Array (PBGA), 25 x 32mm  
1.27mm pitch  
Differential data strobe (DQS, DQS#) per byte  
Internal, pipelined, double data rate architecture  
4-bit prefetch architecture  
DLL for alignment of DQ and DQS transitions with  
clock signal  
Four internal banks for concurrent operation  
(Per DDR2 SDRAM Die)  
47% IꢀO reduction vs Individual ꢁSP approach  
Reduced trace lengths for lower parasitic  
capacitance  
„
„
„
„
„
„
Suitable for hi-reliability applications  
Upgradable to 64M x 64 density  
(consult factory for info on  
AS4DDR264M64PBG)  
„
ConfigurationAddressing  
„
„
„
„
„
„
„
„
„
„
Programmable Burst lengths: 4 or 8  
Auto Refresh and Self Refresh Modes  
On Die Termination (ODT)  
Parameter  
32Megx72  
8Megx16x4Banks  
8K  
Adjustable data – output drive strength  
1.8V 0.1V power supply and IꢀO (VꢁꢁꢀVꢁꢁQ)  
Programmable ꢁAS latency: 3, 4, 5, or 6  
Posted ꢁAS additive latency: 0, 1, 2, 3 or 4  
Write latency = Read latency - 1* tꢁK  
Organized as 32M x 64  
Configuration  
RefreshCount  
RowAddress  
BankAddress  
ColumnAddress  
8K(A0ͲA12)  
4(BA0ͲBA1)  
1K(A0ͲA9)  
Weight: AS4DDR232M64PBG ~ 3.5 grams typical  
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only  
FUNCTIONAL BLOCK DIAGRAM  
Ax, BA0-2  
ODT  
VRef  
VCC  
VCCQ  
VSS  
VSSQ  
VCCL  
VCCL  
VCCL  
VCCL  
VSSDL  
VSSDL  
VSSDL  
VSSDL  
A
B
C
D
2
2
2
2
2
2
2
CS0\  
CS1\  
CS2\  
CS3\  
2
2
2
2
2
3
3
3
3
3
3
3
3
UDMx, LDMx  
UDSQx,UDSQx\  
LDSQx, LDSQx\  
RASx\,CASx\,WEx\  
CKx,CKx\,CKEx  
C
D
B
DQ16-31  
DQ48-63  
A
DQ0-15  
DQ32-47  
Austin Semiconductor, Inc.  
Austin, Texas 512.339.1188 www.austinsemiconductor.com  
AS4DDR232M64PBG  
Rev. 1.3 6/09  
1

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