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AS4C1M16E5-60JC PDF预览

AS4C1M16E5-60JC

更新时间： 2024-02-12 16:43:06
品牌 Logo 应用领域
ALSC 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
22页 601K
描述
5V 1M×16 CMOS DRAM (EDO)

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中文翻译

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AS4C1M16E5-60JC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOJ包装说明：SOJ, SOJ42,.44
针数：42Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.73Is Samacsys：N
访问模式：FAST PAGE WITH EDO最长访问时间：60 ns
其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESHI/O 类型：COMMON
JESD-30 代码：R-PDSO-J42JESD-609代码：e0
长度：27.31 mm内存密度：16777216 bit
内存集成电路类型：EDO DRAM内存宽度：16
功能数量：1端口数量：1
端子数量：42字数：1048576 words
字数代码：1000000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1MX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SOJ
封装等效代码：SOJ42,.44封装形状：RECTANGULAR
封装形式：SMALL OUTLINE电源：5 V
认证状态：Not Qualified刷新周期：1024
座面最大高度：3.76 mm自我刷新：YES
最大待机电流：0.001 A子类别：DRAMs
最大压摆率：0.135 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：DUAL宽度：10.16 mm
Base Number Matches：1

AS4C1M16E5-60JC 数据手册

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AS4C1M16E5  
®
Notes  
1
2
3
4
5
6
Write cycles may be byte write cycles (either LCAS or UCAS active).  
Read cycles may be byte read cycles (either LCAS or UCAS active).  
One CAS must be active (either LCAS or UCAS).  
I
I
, I , I , and I  
are dependent on frequency.  
CC6  
CC1 CC3 CC4  
and I  
depend on output loading. Specified values are obtained with the output open.  
CC1  
CC4  
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal  
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after  
extended periods of bias without clocks (greater than 8 ms).  
7
8
9
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load as described in AC test conditions below.  
T
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .  
IH  
IL  
IH  
IL  
Operation within the t  
(max) limit insures that t  
(max) can be met. t  
(max) is specified as a reference point only. If t  
is greater than the  
RCD  
RAC  
RCD  
RCD  
specified t  
(max) limit, then access time is controlled exclusively by t  
.
CAC  
RCD  
10 Operation within the t  
(max) limit insures that t  
(max) can be met. t (max) is specified as a reference point only. If t  
RAD  
is greater than the  
RAD  
RAC  
RAD  
specified t  
(max) limit, then access time is controlled exclusively by t .  
AA  
RAD  
11 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).  
12 Either t or t must be satisfied for a read cycle.  
RCH  
RRH  
13  
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t  
is referenced from  
OFF  
OFF  
rising edge of RAS or CAS, whichever occurs last.  
, t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.  
14  
t
WCS WCH RWD CWD  
AWD  
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the  
WS  
WH  
cycle. If tRWD ≥ t  
(min), t  
≥ t  
(min) and tAWD ≥ t  
(min), the cycle is a read-write cycle and the data out will contain data read from the  
RWD  
CWD  
CWD  
AWD  
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.  
15 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.  
16 Access time is determined by the longest of t or t or t  
CAA  
CAC  
CPA  
17  
tASC ≥ t to achieve t (min) and t (max) values.  
CP PC CPA  
18 These parameters are sampled and not 100% tested.  
19 These characteristics apply to AS4C1M16E5 5V devices.  
AC test conditions  
- Access times are measured with output reference levels of  
VOH = 2.4V and VOL = 0.4V,  
VIH = 2.4V and VIL = 0.8V  
+5V  
+3.3V  
- Input rise and fall times: 2 ns  
Dout  
R1 = 828Ω  
R1 = 828Ω  
Dout  
*including scope  
and jig capacitance  
100 pF*  
R2 = 295Ω  
50 pF*  
R2 = 295Ω  
GND  
GND  
Figure A: Equivalent output load  
(AS4C1M16E5)  
Figure B: Equivalent output load  
(AS4LC1M16E5)  
Key to switching waveforms  
Rising input  
Falling input  
Undefined output/don’t care  
4/11/01; v.1.0  
Alliance Semiconductor  
P. 8 of 22  
1...567891011...22

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