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AS29LV016BRG-70/ET PDF预览

AS29LV016BRG-70/ET

更新时间： 2024-02-17 12:07:31
品牌 Logo 应用领域
AUSTIN 闪存
页数 文件大小 规格书
40页 402K
描述
16 Megabit (2M x 8-Bit / 1M x 16-Bit) CMOS 3.0 Volt-Only Boot Sector Flash Memory

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中文翻译

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AS29LV016BRG-70/ET 技术参数

生命周期：Transferred零件包装代码：TSOP1
包装说明：MO-142DD, TSOP1-48针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.2
最长访问时间：70 ns其他特性：BOTTOM BOOT BLOCK
备用内存宽度：8启动块：BOTTOM
JESD-30 代码：R-PDSO-G48JESD-609代码：e4
长度：18.4 mm内存密度：16777216 bit
内存集成电路类型：FLASH内存宽度：16
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：105 °C
最低工作温度：-40 °C组织：1MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP1
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL编程电压：3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：PALLADIUM GOLD端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
类型：NOR TYPE宽度：12 mm
Base Number Matches：1

AS29LV016BRG-70/ET 数据手册

 浏览型号AS29LV016BRG-70/ET的Datasheet PDF文件第5页浏览型号AS29LV016BRG-70/ET的Datasheet PDF文件第6页浏览型号AS29LV016BRG-70/ET的Datasheet PDF文件第7页浏览型号AS29LV016BRG-70/ET的Datasheet PDF文件第9页浏览型号AS29LV016BRG-70/ET的Datasheet PDF文件第10页浏览型号AS29LV016BRG-70/ET的Datasheet PDF文件第11页 
COTS PEM  
BOOT SECTOR FLASH  
Austin Semiconductor, Inc.  
AS29LV016  
STANDBY MODE  
RESET#: HARDWARE RESET PIN  
When the system is not reading or writing to the device,  
it can place the device in the standby mode. In this mode,  
current consumption is greatly reduced, and the outputs  
are placed in the high impedance state, independent of  
the OE# input.  
The RESET# pin provides a hardware method of resetting  
the device to reading array data. When the system drives  
the RESET# pin to VIL for at least a period of tRP, the  
device immediately terminates any operation in  
progress, tristates all data output pins, and ignores all  
read/write attempts for the duration of the RESET# pulse.  
The device also resets the internal state machine to  
reading array data. The operation that was interrupted  
should be reinitiated once the device is ready to accept  
another command sequence, to ensure data integrity.  
The device enters the CMOS standby mode when the  
CE# and RESET# pins are both held at VCC 0.3 V.  
(Note that this is a more restricted voltage range than  
VIH.) If CE# and RESET# are held at VIH, but not within  
VCC 0.3 V, the device will be in the standby mode, but  
the standby current will be greater. The device requires  
standard access time (tCE) for read access when the device  
is in either of these standby modes, before it is ready to  
read data.  
Current is reduced for the duration of the RESET# pulse.  
When RESET# is held at VSS 0.3 V, the device draws  
CMOS standby current (ICC4). If RESET# is held at VIL but  
not within VSS 0.3 V, the standby current will be greater.  
If the device is deselected during erasure or programming,  
the device draws active current until the operation is  
completed.  
The RESET# pin may be tied to the system reset circuitry.  
Asystem reset would thus also reset the Flash memory,  
enabling the system to read the boot-up firmware from  
the Flash memory.  
ICC3 and ICC4 represents the standby current specification  
shown in the table in DC Characteristics on page 27.  
If RESET# is asserted during a program or erase  
operation, the RY/BY# pin remains a 0 (busy) until the  
internal reset operation is complete, which requires a time  
of tREADY (during EmbeddedAlgorithms). The system can  
thus monitor RY/BY# to determine whether the reset  
operation is complete. If RESET# is asserted when a  
program or erase operation is not executing (RY/BY# pin  
is 1), the reset operation is completed within a time of  
tREADY (not during EmbeddedAlgorithms). The system can  
read data tRH after the RESET# pin returns to VIH.Refer to  
the tables inAC Characteristics on page 29 for RESET#  
parameters and to Figure 13, on page 30 for the timing  
diagram.  
AUTOMATIC SLEEP MODE  
The automatic sleep mode minimizes Flash device energy  
consumption. The device automatically enables this mode  
when addresses remain stable for tACC + 30 ns. The  
automatic sleep mode is independent of the CE#, WE#,  
and OE# control signals. Standard address access timings  
provide new data when addresses are changed. While in  
sleep mode, output data is latched and always available  
to the system. ICC4 in the DC Characteristics on page 27  
represents the automatic sleep mode current specification.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS29LV016  
Rev. 2.1 10/08  
8
1...567891011...40

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