Freescale Semiconductor, Inc.
VOLUME 13, NUMBER 16
DECEMBER 6, 1999
MICROPROCESSOR REPORT
T H E I N S I D E R S ’ G U I D E T O M I C R O P R O C E S S O R H A R D W A R E
Motorola Cellular DSP Does It All
DSP56690 Integrates M-Core MPU, Supports Multiple Wireless Standards
by Tom R. Halfhill
In terms of both integration and performance, it goes well
beyond two related cellular-baseband chips from Motorola,
the DSP56651 and the DSP56652.
Jet-setters who want to stay in touch won’t have to keep
packing more cell phones than shoes much longer. Motorola’s
new DSP56690 is a highly integrated embedded processor
that supports all of the most common wireless standards
likely to be encountered on a globe-hopping journey.
For the first time, a single chip handles analog cellular as
well as a plethora of digital standards: code-division multiple
access (CDMA), time-division multiple access (TDMA),
global system for mobile communications (GSM), integrated
digital enhanced network (iDEN), general packet radio ser-
vice (GPRS), and even the Iridium satellite network. That
covers all of the first-, second-, and so-called 2.5-generation
wireless-telephony standards worldwide.
But despite the initial excitement over the dream of a
universal wireless phone—Motorola’s announcement re-
ceived widespread press coverage and the company’s stock
jumped 5% in one day—even Motorola doubts there’s a
large enough market for such a product. The extra memory
required to store the software for every standard would
inflate the phone’s cost, and relatively few people are obses-
sively connected globetrotters. Instead, Motorola sees the
DSP56690 as a malleable platform for a multitude of future
cell phones. Motorola can tailor the processor for a single
standard or any combination of standards by adding or
removing on-chip peripherals.
The new chip’s DSP core runs at a clock frequency of
104 MHz, while the microcontroller core runs at 52 MHz.
The core voltage can range from 1.8 to 2.7 V (2.2 V is nomi-
nal), and the I/O voltage can range from 1.8 V to 3.3 V. Moto-
rola will manufacture the initial chips in its 0.25-micron
CDR-3 process and migrate to the 0.18-micron HiPerMOS-6
(see MPR 9/14/98, p. 1) process later next year.
Program RAM
252K
Program ROM
6K
DSP
X-Data ROM
Y-Data ROM
Timer
Layer 1
Encryption
Module
Interrupt
Control
DSP56600
Core
Viterbi
Accelerator
Real-Time
Reference
Dedicated PLL
Baseband
Port I/F
Interrupt
Timer
DMA-1
DMA-2
X-Data RAM
Y-Data RAM
52K
Smartcard
Interface
56K
Shared With MCU
UARTs
(2)
AMPS
Accelerator
MCU-DSP
Interface
Layer 1
Timer
Deep-Sleep
Module
Serial
Peripheral
Interface
Serial Audio
Codec Port
DSP Debug
Clock
Control
Data/Speech
Controller
Bus Interface
One-Wire
Interface
GPRS
The first DSP56690-based phone from Motorola’s
wireless-products group will likely be a GSM-only device
when it debuts in 2H00. Later, Motorola may introduce a
GSM/TDMA or GSM/CDMA combo model, which would
still cover a lot of bases in Europe and the U.S. But Motorola
will probably leave it to another vendor to use the DSP56690
as the Rosetta stone of wireless telephony.
Encryption
GPIO
RAM
92K
IC ID
Module
Test-Control
Module
Watchdog
Timer
ROM
1K
USB
Controller
Clock
Monitor
Dedicated
PLL
M-Core 210
Clock
Amplifier
MCU
Memory
Interface
16-Bit DRAM / Flash
Dedicated PLL
Keypad
Port
A Dual-Core Processor
As Figure 1 shows, the DSP56690 integrates a Motorola
56600 DSP core with an M-Core 210 microcontroller, on-
chip memory for both cores, and a vast array of peripherals.
Figure 1. Light-purple blocks show the DSP56690’s on-chip
peripherals, some of which can be removed to customize the chip.
Article Reprint
For More Information On This Product,
Go to: www.freescale.com
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